Infineon TriCore TC1.6P - AND.LT - Less than Accumulating; AND.LT.U - Less than Accumulating Unsigned

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-37
AND.LT
Less Than Accumulating
AND.LT.U
Less Than Accumulating Unsigned
Description
Calculate the logical AND of D[c][0] and the boolean result of the LT or LT.U operation on the contents of data
register D[a] and either data register D[b] (instruction format RR) or const9 (instruction format RC). Put the result
in D[c][0]. All other bits in D[c] are unchanged. D[a] and D[b] are treated as either 32-bit signed (AND.LT) or
unsigned (AND.LT.U) integers. The const9 value is either sign-extended (AND.LT) or zero-extended (AND.LT.U)
to 32-bits.
AND.LTD[c], D[a], const9 (RC)
D[c] = {D[c][31:1], D[c][0] AND (D[a] < sign_ext(const9))};
AND.LTD[c], D[a], D[b] (RR)
D[c] = {D[c][31:1], D[c][0] AND (D[a] < D[b])};
AND.LT.UD[c], D[a], const9 (RC)
D[c] = {D[c][31:1], D[c][0] AND (D[a] < zero_ext(const9))}; // unsigned
AND.LT.UD[c], D[a], D[b] (RR)
D[c] = {D[c][31:1], D[c][0] AND (D[a] < D[b])}; // unsigned
Status Flags
Examples
and.lt d3, d1, d2
C Not set by these instructions.
V Not set by these instructions.
SV Not set by these instructions.
AV Not set by these instructions.
SAV Not set by these instructions.
31
c
28 27
22
H
21 20
const9
12 11
a
8 7
8B
H
0
31
c
28 27
22
H
20 19
-
18 17
-
16 15
b
12 11
a
8 7
0B
H
0
31
c
28 27
23
H
21 20
const9
12 11
a
8 7
8B
H
0
31
c
28 27
23
H
20 19
-
18 17
-
16 15
b
12 11
a
8 7
0B
H
0