Infineon TriCore TC1.6P User Manual

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-59
CADD
Conditional Add
Description
If the contents of data register D[d] are non-zero, then add the contents of data register D[a] and the contents of
either register D[b] (instruction format RRR) or const9 (instruction format RCR) and put the result in data register
D[c]; otherwise put contents of D[a] in D[c]. The const9 value is sign-extended.
CADDD[c], D[d], D[a], const9 (RCR)
condition = D[d] != 0;
result = ((condition) ? D[a] + sign_ext(const9) : D[a]);
D[c] = result[31:0];
CADDD[c], D[d], D[a], D[b] (RRR)
condition = (D[d] != 0);
result = ((condition) ? D[a] + D[b] : D[a]);
D[c] = result[31:0];
CADDD[a], D[15], const4 (SRC)
Status Flags
If the contents of data register D[15] are non-zero, then add contents of data register D[a] and the contents of
const4 and put the result in data register D[a]; otherwise the contents of D[a] is unchanged. The const4 value is
sign-extended.
condition = (D[15] != 0);
result = ((condition) ? D[a] + sign_ext(const4) : D[a]);
D[a] = result[31:0];
C Not set by this instruction.
V overflow = (result > 7FFFFFFF
H
) OR (result < -80000000
H
);
if (condition) then PSW.V = overflow else PSW.V = PSW.V;
SV if (condition AND overflow) then PSW.SV = 1 else PSW.SV = PSW.SV;
AV advanced_overflow = result[31] ^ result[30];
if (condition) then PSW.AV = advanced_overflow else PSW.AV = PSW.AV;
SAV if (condition AND advanced_overflow) then PSW.SAV = 1 else PSW.SAV = PSW.SAV;
31
c
28 27
d
24 23
00
H
21 20
const9
12 11
a
8 7
AB
H
0
31
c
28 27
d
24 23
00
H
20 19
-
18 17
-
16 15
b
12 11
a
8 7
2B
H
0
15
const4
12 11
a
8 7
8A
H
0

Infineon TriCore TC1.6P Specifications

General

Brand	Infineon
Model	TriCore TC1.6P
Category	Microcontrollers
Language	English