Infineon TriCore TC1.6P - SH.GE - Shift Greater than or Equal; SH.GE.U - Shift Greater than or Equal Unsigned

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-332
SH.GE
Shift Greater Than or Equal
SH.GE.U
Shift Greater Than or Equal Unsigned
Description
Left shift D[c] by one. If the contents of data register D[a] are greater than or equal to the contents of either data
register D[b] (instruction format RR) or const9 (instruction format RC), set the least-significant bit of D[c] to one;
otherwise set the least-significant bit of D[c] to 0. D[a] and D[b] are treated as signed (SH.GE) or unsigned
(SH.GE.U) integers. The value const9 is sign-extended (SH.GE) or zero-extended (SH.GE.U).
SH.GED[c], D[a], const9 (RC)
D[c] = {D[c][30:0], (D[a] >= sign_ext(const9))};
SH.GED[c], D[a], D[b] (RR)
D[c] = {D[c][30:0], (D[a] >= D[b])};
SH.GE.UD[c], D[a], const9 (RC)
D[c] = {D[c][30:0], (D[a] >= zero_ext(const9))}; // unsigned
SH.GE.UD[c], D[a], D[b] (RR)
D[c] = {D[c][30:0], (D[a] >= D[b])}; // unsigned
Status Flags
Examples
sh.ge d3, d1, d2
sh.ge d3, d1, #126
C Not set by these instructions.
V Not set by these instructions.
SV Not set by these instructions.
AV Not set by these instructions.
SAV Not set by these instructions.
31
c
28 27
3B
H
21 20
const9
12 11
a
8 7
8B
H
0
31
c
28 27
3B
H
20 19
-
18 17
-
16 15
b
12 11
a
8 7
0B
H
0
31
c
28 27
3C
H
21 20
const9
12 11
a
8 7
8B
H
0
31
c
28 27
3C
H
20 19
-
18 17
-
16 15
b
12 11
a
8 7
0B
H
0