Infineon TriCore TC1.6P - Page 333

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-286
D[c] = {result_halfword1[31:16], result_halfword0[31:16]}; // Packed short fraction
MULR.HD[c], D[a], D[b] UU, n (RR1)
(16L * 16U || 16U * 16U) rounded --> 16||16
sc1 = (D[a][15:0] == 8000
H
) AND (D[b][31:16] == 8000
H
) AND (n == 1);
sc0 = (D[a][31:16] == 8000
H
) AND (D[b][31:16] == 8000
H
) AND (n == 1);
result_halfword1 = sc1 ? 7FFFFFFF
H
: (((D[a][15:0] * D[b][31:16]) << n) + 8000
H
);
result_halfword0 = sc0 ? 7FFFFFFF
H
: (((D[a][31:16] * D[b][31:16]) << n) + 8000
H
);
D[c] = {result_halfword1[31:16], result_halfword0[31:16]}; // Packed short fraction
Status Flags
Examples
-
See Also
-
C Not set by this instruction.
V The PSW.V status bit is cleared.
SV Not set by this instruction.
AV aov_halfword1 = result_halfword1[31] ^ result_halfword1[30];
aov_halfword0 = result_halfword0[31] ^ result_halfword0[30];
advanced_overflow = aov_halfword1 OR aov_halfword0;
if (advanced_overflow) then PSW.AV = 1 else PSW.AV = 0;
SAV if (advanced_overflow) then PSW.SAV = 1 else PSW.SAV = PSW.SAV;
31
c
28 27
0F
H
18 17
n
16 15
b
12 11
a
8 7
B3
H
0