Infineon TriCore TC1.6P - Page 325

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-278
result = ((D[a] * D[b][31:16]) << n) >> 16;
D[c] = result[31:0];// Fraction
MUL.QE[c], D[a], D[b] U, n (RR1)
(32 * 16U) --> 64
result = (D[a] * D[b][31:16]) << n;
E[c] = result[63:0]; // Multi-precision accumulator
MUL.QD[c], D[a] L, D[b] L, n (RR1)
(16L * 16L) --> 32
sc = (D[a][15:0] == 8000
H
) AND (D[b][15:0] == 8000
H
) AND (n == 1);
result = sc ? 7FFFFFFF
H
: ((D[a][15:0] * D[b][15:0]) << n);
D[c] = result[31:0]; // Fraction
MUL.QD[c], D[a] U, D[b] U, n (RR1)
(16U * 16U) --> 32
sc = (D[a][31:16] == 8000
H
) AND (D[b][31:16] == 8000
H
) AND (n == 1);
result = sc ? 7FFFFFFF
H
: ((D[a][31:16] * D[b][31:16]) << n);
D[c] = result[31:0]; // Fraction
Status Flags
C Not set by this instruction.
V 32-bit result:
overflow = (result > 7FFFFFFF
H
) OR (result < -80000000
H
);
if (overflow) then PSW.V = 1 else PSW.V = 0;
64-bit result:
overflow = (result > 7FFFFFFFFFFFFFFF
H
) OR (result < -8000000000000000
H
);
if (overflow) then PSW.V = 1 else PSW.V = 0;
SV if (overflow) then PSW.SV = 1 else PSW.SV = PSW.SV;
31
c
28 27
00
H
18 17
n
16 15
b
12 11
a
8 7
93
H
0
31
c
28 27
18
H
18 17
n
16 15
b
12 11
a
8 7
93
H
0
31
c
28 27
05
H
18 17
n
16 15
b
12 11
a
8 7
93
H
0
31
c
28 27
04
H
18 17
n
16 15
b
12 11
a
8 7
93
H
0