Infineon TriCore TC1.6P - Page 211

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-164
A[b+1] = {length[15:0], new_index[15:0]};
LD.HUD[a], A[b], off10 (BO)(Post-increment Addressing Mode)
EA = A[b];
D[a] = zero_ext(M(EA, halfword));
A[b] = EA + sign_ext(off10);
LD.HUD[a], A[b], off10 (BO)(Pre-increment Addressing Mode)
EA = A[b] + sign_ext(off10);
D[a] = zero_ext(M(EA, halfword));
A[b] = EA;
LD.HUD[a], A[b], off16 (BOL)(Base + Long Offset Addressing Mode)
EA = A[b] + sign_ext(off16);
D[a] = zero_ext(M(EA, halfword));
Status Flags
Examples
ld.h d0, [a0]
ld.hu d1, [a0]
See Also
LD.A, LD.B, LD.BU, LD.D, LD.DA, LD.Q, LD.W
C Not set by this instruction.
V Not set by this instruction.
SV Not set by this instruction.
AV Not set by this instruction.
SAV Not set by this instruction.
31
off10[9:6]
28 27
03
H
22 21
off10[5:0]
16 15
b
12 11
a
8 7
09
H
0
31
off10[9:6]
28 27
13
H
22 21
off10[5:0]
16 15
b
12 11
a
8 7
09
H
0
31
off16[9:6]
28 27
off16[15:10]
22 21
off16[5:0]
16 15
b
12 11
a
8 7
B9
H
0