Infineon TriCore TC1.6P - Page 198

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-151
new_index = new_index < 0 ? new_index+length : new_index % length;
A[b+1] = {length[15:0], new_index[15:0]};
LD.AA[a], A[b], off10 (BO)(Post-increment Addressing Mode)
EA = A[b];
A[a] = M(EA, word);
A[b] = EA + sign_ext(off10);
LD.AA[a], A[b], off10 (BO)(Pre-increment Addressing Mode)
EA = A[b] + sign_ext(off10);
A[a] = M(EA, word);
A[b] = EA;
LD.AA[a], A[b], off16 (BOL)(Base + Long Offset Addressing Mode)
EA = A[b] + sign_ext(off16);
A[a] = M(EA, word);
LD.AA[15], A[10], const8 (SC)
LD.AA[c], A[b] (SLR)
LD.AA[c], A[b] (SLR)(Post-increment Addressing Mode)
A[15] = M(A[10] + zero_ext(4 * const8), word);
A[c] = M(A[b], word);
31
off10[9:6]
28 27
06
H
22 21
off10[5:0]
16 15
b
12 11
a
8 7
09
H
0
31
off10[9:6]
28 27
16
H
22 21
off10[5:0]
16 15
b
12 11
a
8 7
09
H
0
31
off16[9:6]
28 27
off16[15:10]
22 21
off16[5:0]
16 15
b
12 11
a
8 7
99
H
0
15
const8
8 7
D8
H
0
15
b
12 11
c
8 7
D4
H
0
15
b
12 11
c
8 7
C4
H
0