Infineon TriCore TC1.6P - Page 209

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-162
new_index = index + sign_ext(off10);
new_index = new_index < 0 ? new_index + length : new_index % length;
A[b+1] = {length[15:0], new_index[15:0]};
LD.HD[a], A[b], off10 (BO)(Post-increment Addressing Mode)
EA = A[b];
D[a] = sign_ext(M(EA, halfword));
A[b] = EA + sign_ext(off10);
LD.HD[a], A[b], off10 (BO)(Pre-increment Addressing Mode)
EA = A[b] + sign_ext(off10);
D[a] = sign_ext(M(EA, halfword));
A[b] = EA;
LD.HD[a], A[b], off16 (BOL)(Base + Long Offset Addressing Mode)
EA = A[b] + sign_ext(off16);
D[a] = sign_ext(M(EA, halfword));
LD.HD[c], A[b] (SLR)
LD.HD[c], A[b] (SLR)(Post-increment Addressing Mode)
LD.HD[c], A[15], off4 (SLRO)
D[c] = sign_ext(M(A[b], halfword));
D[c] = sign_ext(M(A[b], half-word));
A[b] = A[b] + 2;
31
off10[9:6]
28 27
02
H
22 21
off10[5:0]
16 15
b
12 11
a
8 7
09
H
0
31
off10[9:6]
28 27
12
H
22 21
off10[5:0]
16 15
b
12 11
a
8 7
09
H
0
31
off16[9:6]
28 27
off16[15:10]
22 21
off16[5:0]
16 15
b
12 11
a
8 7
C9
H
0
15
b
12 11
c
8 7
94
H
0
15
b
12 11
c
8 7
84
H
0
15
off4
12 11
c
8 7
88
H
0