Infineon TriCore TC1.6P - Page 231

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-184
result = D[d] + (D[a] * sign_ext(const9));
D[c] = ssov(result, 32);
MADDSE[c], E[d], D[a], const9 (RCR)
64 + (32 * K9)--> 64 signed saturated
result = E[d] + (D[a] * sign_ext(const9));
E[c]= ssov(result, 64);
MADDSD[c], D[d], D[a], D[b] (RRR2)
32 + (32 * 32)--> 32 signed saturated
result = D[d] + (D[a] * D[b]);
D[c] = ssov(result, 32);
MADDSE[c], E[d], D[a], D[b] (RRR2)
64 + (32 * 32)--> 64 signed saturated
result = E[d] + (D[a] * D[b]);
E[c] = ssov(result, 64);
Status Flags
C Not set by these instructions.
V 32-bit result:
overflow = (result > 7FFFFFFF
H
) OR (result < -80000000
H
);
if (overflow) then PSW.V = 1 else PSW.V = 0;
64-bit result:
overflow = (result > 7FFFFFFFFFFFFFFF
H
) OR (result < -8000000000000000
H
);
if (overflow) then PSW.V = 1 else PSW.V = 0;
SV if (overflow) then PSW.SV = 1 else PSW.SV = PSW.SV;
AV 32-bit result:
advanced_overflow = result[31] ^ result[30];
if (advanced_overflow) then PSW.AV = 1 else PSW.AV = 0;
64-bit result:
advanced_overflow = result[63] ^ result[62];
if (advanced_overflow) then PSW.AV = 1 else PSW.AV = 0;
31
c
28 27
d
24 23
05
H
21 20
const9
12 11
a
8 7
13
H
0
31
c
28 27
d
24 23
07
H
21 20
const9
12 11
a
8 7
13
H
0
31
c
28 27
d
24 23
8A
H
16 15
b
12 11
a
8 7
03
H
0
31
c
28 27
d
24 23
EA
H
16 15
b
12 11
a
8 7
03
H
0