Infineon TriCore TC1.6P - Page 235

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-188
result_word0 = E[d][31:0] + mul_res0;
E[c] = {ssov(result_word1, 32), ssov(result_word0, 32)}; // Packed fraction
MADDS.HE[c], E[d], D[a], D[b] UL, n (RRR1)
32||32 +||+ (16U * 16U || 16L * 16L)--> saturated
sc1 = (D[a][31:16] == 8000
H
) AND (D[b][31:16] == 8000
H
) AND (n == 1);
sc0 = (D[a][15:0] == 8000
H
) AND (D[b][15:0] == 8000
H
) AND (n == 1);
mul_res1 = sc1 ? 7FFFFFFF
H
: ((D[a][31:16] * D[b][31:16]) << n);
mul_res0 = sc0 ? 7FFFFFFF
H
: ((D[a][15:0] * D[b][15:0]) << n);
result_word1 = E[d][63:32] + mul_res1;
result_word0 = E[d][31:0] + mul_res0;
E[c] = {ssov(result_word1, 32), ssov(result_word0, 32)}; // Packed fraction
MADDS.HE[c], E[d], D[a], D[b] UU, n (RRR1)
32||32 +||+ (16L * 16U || 16U * 16U)--> 32||32 saturated
sc1 = (D[a][15:0] == 8000
H
) AND (D[b][31:16] == 8000
H
) AND (n == 1);
sc0 = (D[a][31:16] == 8000
H
) AND (D[b][31:16] == 8000
H
) AND (n == 1);
mul_res1 = sc1 ? 7FFFFFFF
H
: ((D[a][15:0] * D[b][31:16]) << n);
mul_res0 = sc0 ? 7FFFFFFF
H
: ((D[a][31:16] * D[b][31:16]) << n);
result_word1 = E[d][63:32] + mul_res1;
result_word0 = E[d][31:0] + mul_res0;
E[c] = {ssov(result_word1, 32), ssov(result_word0, 32)}; // Packed fraction
Status Flags
Examples
-
C Not set by these instructions.
V ov_word1 = (result_word1 > 7FFFFFFF
H
) OR (result_word1 < -80000000
H
);
ov_word0 = (result_word0 > 7FFFFFFF
H
) OR (result_word0 < -80000000
H
);
overflow = ov_word1 OR ov_word0;
if (overflow) then PSW.V = 1 else PSW.V = 0;
SV if (overflow) then PSW.SV = 1 else PSW.SV = PSW.SV;
AV aov_word1 = result_word1[31] ^ result_word1[30];
aov_word0 = result_word0[31] ^ result_word0[30];
advanced_overflow = aov_word1 OR aov_word0;
if (advanced_overflow) then PSW.AV = 1 else PSW.AV = 0;
SAV if (advanced_overflow) then PSW.SAV = 1 else PSW.SAV = PSW.SAV;
31
c
28 27
d
24 23
38
H
18 17
n
16 15
b
12 11
a
8 7
83
H
0
31
c
28 27
d
24 23
3B
H
18 17
n
16 15
b
12 11
a
8 7
83
H
0