Infineon TriCore TC1.6P - Page 241

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-194
64 + (16U * 16U) --> 64 saturated
sc = (D[a][31:16] == 8000
H
) AND (D[b][31:16] == 8000
H
) AND (n == 1);
mul_res = sc ? 7FFFFFFF
H
: ((D[a][31:16] * D[b][31:16]) << n);
result = E[d] + (mul_res << 16);
E[c] = ssov(result, 64); // Multi-precision accumulator
Status Flags
Examples
madd.q d0, d1, d2, d3, #1
madd.q d0, d1, d2, d6U, #1
madd.q d0, d2, d1, d3L, #1
madd.q d2, d0, d3U, d4U, #1
madd.q d2, d0, d4L, d4L, #1
madd.q e2, e2, d3, d7, #1
madd.q e2, e2, d4, d6U, #1
madd.q e2, e2, d5, d6L, #1
madd.q e2, e2, d6U, d7U, #1
madd.q e2, e2, d8L, d0L, #1
madds.q d0, d1, d2, d3, #1
madds.q d0, d1, d2, d6U, #1
madds.q d0, d2, d1, d3L, #1
madds.q d2, d0, d3U, d4U, #1
madds.q d2, d0, d4L, d4L, #1
madds.q e2, e2, d3, d7, #1
madds.q e2, e2, d4, d6U, #1
madds.q e2, e2, d5, d6L, #1
madds.q e2, e2, d6U, d7U, #1
madds.q e2, e0, d11L, d4L, #1
C Not set by these instructions.
V 32-bit result:
overflow = (result > 7FFFFFFF
H
) OR (result < -80000000
H
);
if (overflow) then PSW.V = 1 else PSW.V = 0;
64-bit result:
overflow = (result > 7FFFFFFFFFFFFFFF
H
) OR (result < -8000000000000000
H
);
if (overflow) then PSW.V = 1 else PSW.V = 0;
SV if (overflow) then PSW.SV = 1 else PSW.SV = PSW.SV;
AV 32-bit result:
advanced_overflow = result[31] ^ result[30];
if (advanced_overflow) then PSW.AV = 1 else PSW.AV = 0;
64-bit result:
advanced_overflow = result[63] ^ result[62];
if (advanced_overflow) then PSW.AV = 1 else PSW.AV = 0;
SAV if (advanced_overflow) then PSW.SAV = 1 else PSW.SAV = PSW.SAV;
31
c
28 27
d
24 23
3C
H
18 17
n
16 15
b
12 11
a
8 7
43
H
0