Infineon TriCore TC1.6P - Page 263

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-216
sc0 = (D[a][15:0] == 8000
H
) AND (D[b][31:16]] == 8000
H
) AND (n == 1);
mul_res1 = sc1 ? 7FFFFFFF
H
: ((D[a][31:16] * D[b][15:0]) << n);
mul_res0 = sc0 ? 7FFFFFFF
H
: ((D[a][15:0] * D[b][31:16]) << n);
result_halfword1 = {D[d][31:16], 16’b0} + mul_res1 + 8000
H
;
result_halfword0 = {D[d][15:0], 16’b0} - mul_res0 + 8000
H
;
D[c] = {ssov(result_halfword1, 32)[31:16], ssov(result_halfword0, 32)[31:16]};
// Packed short fraction result
MADDSURS.HD[c], D[d], D[a], D[b] UL, n (RRR1)
16U || 16L +||- (16U * 16U || 16L * 16L) rounded --> 16||16 saturated
sc1 = (D[a][31:16] == 8000
H
) AND (D[b][31:16] == 8000
H
) AND (n == 1);
sc0 = (D[a][15:0] == 8000
H
) AND (D[b][15:0] == 8000
H
) AND (n == 1);
mul_res1 = sc1 ? 7FFFFFFF
H
: ((D[a][31:16] * D[b][31:16]) << n);
mul_res0 = sc0 ? 7FFFFFFF
H
: ((D[a][15:0] * D[b][15:0]) << n);
result_halfword1 = {D[d][31:16], 16’b0} + mul_res1 + 8000
H
;
result_halfword0 = {D[d][15:0], 16’b0} - mul_res0 + 8000
H
;
D[c] = {ssov(result_halfword1, 32)[31:16], ssov(result_halfword0, 32)[31:16]};
// Packed short fraction result
MADDSURS.HD[c], D[d], D[a], D[b] UU, n (RRR1)
16U || 16L +||- (16L * 16U || 16U * 16U) rounded --> 16||16 saturated
sc1 = (D[a][15:0] == 8000
H
) AND (D[b][31:16] == 8000
H
) AND (n == 1);
sc0 = (D[a][31:16] == 8000
H
) AND (D[b][31:16]] == 8000
H
) AND (n == 1);
mul_res1 = sc1 ? 7FFFFFFF
H
: ((D[a][15:0] * D[b][31:16]) << n);
mul_res0 = sc0 ? 7FFFFFFF
H
: ((D[a][31:16] * D[b][31:16]) << n);
result_halfword1 = {D[d][31:16], 16’b0} + mul_res1 + 8000
H
;
result_halfword0 = {D[d][15:0], 16’b0} - mul_res0 + 8000
H
;
D[c] = {ssov(result_halfword1, 32)[31:16], ssov(result_halfword0, 32)[31:16]};
// Packed short fraction result
Status Flags
C Not set by these instructions.
31
c
28 27
d
24 23
2C
H
18 17
n
16 15
b
12 11
a
8 7
C3
H
0
31
c
28 27
d
24 23
2F
H
18 17
n
16 15
b
12 11
a
8 7
C3
H
0