Infineon TriCore TC1.6P - Page 297

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-250
result = D[d] - (D[a] * D[b]); // unsigned operators
D[c]= suov(result, 32);
MSUBS.UE[c], E[d], D[a], D[b] (RRR2)
64 - (32 * 32) --> 64 unsigned saturated
result = E[d] - (D[a] * D[b]); // unsigned operators
E[c] = suov(result, 64);
Status Flags
Examples
msub.u e0, e2, d6, d11
msub.u e0, e0, d3, #80
msubs.u d5, d1, d2, d2
msubs.u d1, d1, d2, #7
msubs.u e0, e2, d6, d11
msubs.u e8, e4, d3, #80
See Also
-
C Not set by these instructions.
V 32-bit result:
overflow = (result > FFFFFFFF
H
) OR (result < 00000000
H
);
if (overflow) then PSW.V = 1 else PSW.V = 0;
64-bit result:
overflow = (result > FFFFFFFFFFFFFFFF
H
) OR (result < 0000000000000000
H
);
if (overflow) then PSW.V = 1 else PSW.V = 0;
SV if (overflow) then PSW.SV = 1 else PSW.SV = PSW.SV;
AV 32-bit result:
advanced_overflow = result[31] ^ result[30];
if (advanced_overflow) then PSW.AV = 1 else PSW.AV = 0;
64-bit result:
advanced_overflow = result[63] ^ result[62];
if (advanced_overflow) then PSW.AV = 1 else PSW.AV = 0;
SAV if (advanced_overflow) then PSW.SAV = 1 else PSW.SAV = PSW.SAV;
31
c
28 27
d
24 23
88
H
16 15
b
12 11
a
8 7
23
H
0
31
c
28 27
d
24 23
E8
H
16 15
b
12 11
a
8 7
23
H
0