TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-268
mul_res0 = sc0 ? 7FFFFFFF
H
: ((D[a][15:0] * D[b][15:0]) << n);
result_halfword1 = E[d][63:32] - mul_res1 + 8000
H
;
result_halfword0 = E[d][31:0] - mul_res0 + 8000
H
;
D[c] = {ssov(result_halfword1, 32)[31:16], ssov(result_halfword0, 32)[31:16]};
// Packed short fraction result
MSUBRS.HD[c], D[d], D[a], D[b] UU, n (RRR1)
16U || 16L -||- (16L * 16U || 16U * 16U) rounded --> 16||16 saturated
sc1 = (D[a][15:0] == 8000
H
) AND (D[b][31:16] == 8000
H
) AND (n == 1);
sc0 = (D[a][31:16] == 8000
H
) AND (D[b][31:16] == 8000
H
) AND (n == 1);
mul_res1 = sc1 ? 7FFFFFFF
H
: ((D[a][15:0] * D[b][31:16]) << n);
mul_res0 = sc0 ? 7FFFFFFF
H
: ((D[a][31:16] * D[b][31:16]) << n);
result_halfword1 = {D[d][31:16], 16’b0} - mul_res1 + 8000
H
;
result_halfword0 = {D[d][15:0], 16’b0} - mul_res0 + 8000
H
;
D[c] = {ssov(result_halfword1, 32)[31:16], ssov(result_halfword0, 32)[31:16]};
// Packed short fraction result
Status Flags
Examples
-
See Also
-
C Not set by these instructions.
V ov_halfword1 = (result_halfword1 > 7FFFFFFF
H
) OR (result_halfword1 < -80000000
H
);
ov_halfword0 = (result_halfword0 > 7FFFFFFF
H
) OR (result_halfword0 < -80000000
H
);
overflow = ov_halfword1 OR ov_halfword0;
if (overflow) then PSW.V = 1 else PSW.V = 0;
SV if (overflow) then PSW.SV = 1 else PSW.SV = PSW.SV;
AV aov_overflow1 = result_halfword1[31] ^ result_halfword1[30];
aov_overflow0 = result_halfword0[31] ^ result_halfword0[30];
advanced_overflow = aov_overflow1 OR aov_overflow0;
if (advanced_overflow) then PSW.AV = 1 else PSW.AV = 0;
SAV if (advanced_overflow) then PSW.SAV = 1 else PSW.SAV = PSW.SAV;
31
c
28 27
d
24 23
2F
H
18 17
n
16 15
b
12 11
a
8 7
A3
H
0
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