Infineon TriCore TC1.6P - Page 328

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-281
Examples
mul.u e0, d2, d3
muls.u d3, d5, d9
See Also
MUL
V 32-bit result:
overflow = (result > FFFFFFFF
H
) OR (result < 00000000
H
);
if (overflow) then PSW.V = 1 else PSW.V = 0;
64-bit result:
It is mathematically impossible to generate an overflow when multiplying two 32-bit numbers and storing
the result in a 64-bit register.
SV if (overflow) then PSW.SV = 1 else PSW.SV = PSW.SV;
AV 32-bit result:
advanced_overflow = result[31] ^ result[30];
if (advanced_overflow) then PSW.AV = 1 else PSW.AV = 0;
64-bit result:
advanced_overflow = result[63] ^ result[62];
if (advanced_overflow) then PSW.AV = 1 else PSW.AV = 0;
SAV if (advanced_overflow) then PSW.SAV = 1 else PSW.SAV = PSW.SAV;