TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-357
A[b+1] = {length[15:0], new_index[15:0]};
ST.HA[b], off10, D[a] (BO)(Post-increment Addressing Mode)
EA = A[b];
M(EA, halfword) = D[a][15:0];
A[b] = EA + sign_ext(off10);
ST.HA[b], off10, D[a] (BO)(Pre-increment Addressing Mode)
EA = A[b] + sign_ext(off10);
M(EA, halfword) = D[a][15:0];
A[b] = EA;
ST.HA[b], off16, D[a] (BOL)(Base + Long Offset Addressing Mode)
EA = A[b] + sign_ext(off16);
M(EA, halfword) = D[a][15:0];
ST.HA[b], off4, D[15] (SRO)
ST.HA[b], D[a] (SSR)
ST.HA[b], D[a] (SSR)(Post-increment Addressing Mode)
M(A[b] + zero_ext(2 * off4), half-word) = D[15][15:0];
M(A[b], half-word) = D[a][15:0];
M(A[b], half-word) = D[a][15:0];
A[b] = A[b] + 2;
31
off10[9:6]
28 27
02
H
22 21
off10[5:0]
16 15
b
12 11
a
8 7
89
H
0
31
off10[9:6]
28 27
12
H
22 21
off10[5:0]
16 15
b
12 11
a
8 7
89
H
0
31
off16[9:6]
28 27
off16[15:10]
22 21
off16[5:0]
16 15
b
12 11
a
8 7
F9
H
0