Revision history RM0033
1356/1381 RM0033 Rev 9
15-Apr-2011 3
Updated OTP area in Section 2.3.3: Embedded Flash memory.
Modified Section : Embedded bootloader.
Changed f
MASTER
to CK_INT in the whole document.
Modified DAC bus in Table 1: STM32F20x and STM32F21x register
boundary addresses.
PWR:
Added note related to voltage regulator activation depending to
package in Section 4.1.3: Voltage regulator.
RCC:
Added note related to I2S PLL used as I2S input clock in
Section 5.2.3: PLL configuration.
Modified VCO output frequency for PLLN bit description in
Section 5.3.2: RCC PLL configuration register (RCC_PLLCFGR).
GPIOs:
Removed RTF_AF1 and RTC_AF2 from system functions in
Section 6.3.2: I/O pin multiplexer and mapping.
Modified Section 6.3.13: Using the OSC32_IN/OSC32_OUT pins as
GPIO PC14/PC15 port pins and Section 6.3.14: Using the
OSC_IN/OSC_OUT pins as GPIO PH0/PH1 port pins
TIMERS:
TIM1&TIM8: Updated example and definition of DBL bits in
Section 13.4.19: TIM1 and TIM8 DMA control register (TIMx_DCR).
Added example related to DMA burst feature and description of
DMAB bits in Section 13.4.20: TIM1 and TIM8 DMA address for full
transfer (TIMx_DMAR).
TIM2 to TIM5: added example and updated definition of DBL bits in
Section 14.4.17: TIMx DMA control register (TIMx_DCR). Added
example related to DMA burst feature and description of DMAB bits
in Section 14.4.18: TIMx DMA address for full transfer
(TIMx_DMAR).
IWDG:
Modified LSI clock frequency in Table 69: Min/max IWDG timeout
period (in ms) at 32 kHz (LSI) title and updated timeout values.
WWDG:
Updated Section 18.2: WWDG main features.
Updated Section 18.3: WWDG functional description to remove
paragraph related to counter reload using EWI interrupt.
Added Section : Advanced watchdog interrupt featurein
Section 18.4: How to program the watchdog timeout.
Table 224. Document revision history (continued)
Date Version Changes
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