Revision history RM0033
1368/1381 RM0033 Rev 9
04-Feb-2015 7
PWR
Updated Table 7: Low-power mode summary to add Return from ISR
as entry condition.
Added Section : Entering low-power mode and Section : Exiting low-
power mode.
Updated Section : Entering Sleep mode, Section : Exiting Sleep
mode, Table 8: Sleep-now and Table 9: Sleep-on-exit.
Updated Section : Entering Stop mode, Section : Exiting Stop mode,
and Table 10: Stop mode.
Updated Section : Entering Standby mode, Section : Exiting Standby
mode and Table 11: Standby mode.
RCC
Updated caution note applying to PLLN in Section 5.3.2: RCC PLL
configuration register (RCC_PLLCFGR).
Changed bits 25 to 31 access type to ‘r’ and bit 24 (RMVF) to ‘rt_w’
in Section 5.3.21: RCC clock control & status register (RCC_CSR)
DMA
Updated Section 9.3.7: Pointer incrementation and Section 9.3.11:
Single and burst transfers.
Updated FTH[1:0] description in Section 9.5.10: DMA stream x FIFO
control register (DMA_SxFCR) (x = 0..7).
ADC
Updated Section 10.3.10: Discontinuous mode.
DCMI
Updated Section 12.4: DCMI clocks and Section 12.5.2: DCMI
physical interface
TIM1/8
Updated CCPC definition in Section 13.4.2: TIM1 and TIM8 control
register 2 (TIMx_CR2)
TIM2 to TIM5
Replaced IC2S by CC2S. Updated Figure 140: Output stage of
capture/compare channel (channel 1).
TIM9 to TIM14
Added Section 15.5.2: TIM10/11/13/14 Interrupt enable register
(TIMx_DIER). Updated Table 63: TIMx internal trigger connection.
Added Section 15.5.2: TIM10/11/13/14 Interrupt enable register
(TIMx_DIER).
WDGLS
Update note in Table 69: Min/max IWDG timeout period (in ms) at 32
kHz (LSI).
Table 224. Document revision history (continued)
Date Version Changes
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