Revision history RM0033
1370/1381 RM0033 Rev 9
26-Apr-2018 8
Added Arm logo and notice in Section 1: Documentation conventions
and changed ‘ARM’ wordmark to ‘Arm’ in the whole document.
RCC
Changed OTG_HS_SCL into OTG_HS_ULPI_CK in Figure 9: Clock
tree.
GPIOs
Changed definition of OSPEEDR bits in Section 6.4.3: GPIO port
output speed register (GPIOx_OSPEEDR) (x = A..I).
DMA
Changed bit 18 of DMS_SxCR to DBM in register bit map table.
Changed bit 20 from ACK to reserved in Table 31: DMA register map
and reset values.
ADC
Updated DMA mode 1 and DMA mode 3 description in Section 10.9:
Multi ADC mode.
DAC
Replaced 4095 by 4096 in formula in Section 11.3.5: DAC output
voltage.
TIM1 and TIM8
Updated Section 13.3.21: Debug mode.
Added note related to slave clock in MMS bits of TMIx_CR2.
Extended TIMx_DMAR to 32 bits.
Changed TIMx_ARR reset value to 0xFFFF.
Updated Table 57: Output control bits for complementary OCx and
OCxN channels with break feature output state for MOE = 0.
Updated SMS bit description in TIMx_SMCR and added note related
to slave clock. Updated Table 56: TIMx Internal trigger connection.
TIM2 to TIM5
Added note related to the slave timer clock in Section 14.3.15: Timer
synchronization.
Updated SMS bit description in TIMx_SMCR and added note related
to slave clock.
Added note related to slave clock in MMS bits of TMIx_CR2.
Updated Section 14.4.11: TIMx prescaler (TIMx_PSC).
Changed TIMx_ARR reset value to 0xFFFF.
Changed TIMx_ARR reset value to 0xFFFF.
Table 224. Document revision history (continued)
Date Version Changes
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