RM0033 Rev 9 1371/1381
RM0033 Revision history
1375
26-Apr-2018
8
(continued)
TIM9 to 14
Updated Section 15.4.3: TIM9/12 slave mode control register
(TIMx_SMCR) encoder mode description and adding note on
bits[2:0] for the slave timer clock.
Updated TIMx_SMCR and TIMx_CCMR1 register adding
“consecutive” in the description.
Updated Section 15.4.10: TIM9/12 prescaler (TIMx_PSC).
Added OPM bit in Section 15.5.1: TIM10/11/13/14 control register 1
(TIMx_CR1)
Changed TIMx_ARR reset value to 0xFFFF.
TIM6 and TIM7
Updated Section 16.4.7: TIM6 and TIM7 prescaler (TIMx_PSC)
Changed TIMx_ARR reset value to 0xFFFF.
WWDG
Figure 193: Watchdog block diagram replacing 6-bit downcounter by
7-bit. downcounter..
HASH
HASH availability restricted to STM32F21xx devices.
RTC
Updated WUCKSEL prescaler input in Figure 215: RTC block
diagram.
Updated 3rd step in Section : Programming the wakeup timer.
Updated Section 22.3.7: Resetting the RTC.
Updated Section 22.3.8: RTC reference clock detection.
Added note for WUFE bit in Section 22.6.3: RTC control register
(RTC_CR).
Updated WUTWF bit definition in Section 22.6.4: RTC initialization
and status register (RTC_ISR).
I2C
Updated FREQ[5:0] description in Section 23.6.2: I
2
C Control
register 2 (I2C_CR2) to make it generic for all products.
USART
Replaced all occurrences of
– nCTS by CTS
– nRTS by RTS
– SCLK by CK
Removed note related to RXNEIE in Section : Reception using DMA.
Added note in ONEBIT description in Section 24.6.6: Control register
3 (USART_CR3).
Table 224. Document revision history (continued)
Date Version Changes
To Next Page
Loading...
Need help?
General
