RM0033 Rev 9 1375/1381
RM0033 Revision history
1375
25-Feb-2021
9
(continued)
– Section 28: Ethernet (ETH): media access control (MAC) with
DMA controller:
Section : Normal Tx DMA descriptors
– Section 29: USB on-the-go full-speed (OTG_FS):
Table 153: Device-mode control and status registers
Section 29.17.6: Operational model
– Section 30: USB on-the-go high-speed (OTG_HS):
Section : Detection of peripheral connection by the host
Table 161: Core global control and status registers (CSRs)
Table 163: Device-mode control and status registers
Section : OTG_HS device IN endpoint transmit FIFO size register
(OTG_HS_DIEPTXFx) (x = 1..5, where x is the FIFO_number)
Section : OTG_HS all endpoints interrupt mask register
(OTG_HS_DAINTMSK)
Section : OTG device endpoint-x control register
(OTG_HS_DIEPCTLx) (x = 0..5, where x = Endpoint_number)
Section : OTG_HS device endpoint-x control register
(OTG_HS_DOEPCTLx) (x = 1..5, where x = Endpoint_number)
Section : OTG_HS device endpoint-x interrupt register
(OTG_HS_DIEPINTx) (x = 0..5, where x = Endpoint_number)
Section : OTG_HS device endpoint-x interrupt register
(OTG_HS_DOEPINTx) (x = 0..5, where x = Endpoint_number)
Section : OTG_HS device endpoint-x transfer size register
(OTG_HS_DIEPTSIZx) (x = 1..5, where x = Endpoint_number)
Section : OTG_HS device endpoint-x DMA address register
(OTG_HS_DIEPDMAx / OTG_HS_DOEPDMAx) (x = 0..5, where
x = Endpoint_number)
Table 168: OTG_HS register map and reset values
Section 30.13.2: Host initialization
Figure 379: Transmit FIFO write task
Figure 380: Receive FIFO read task
Figure 389: Receive FIFO packet read in slave mode
Figure 390: Processing a SETUP packet
Section 30.13.7: Operational model
– Section 32: Debug support (DBG):
Section 32.6.1: MCU device ID code
Table 224. Document revision history (continued)
Date Version Changes
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