ARM CoreLink GIC-600AE

Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
Record GICT_ERR<n>STATUS.IERR (syndrome) GICT_ERR<n>STATUS
.SERR
Value and description of
GICT_ERR<n>MISC0.Data (other bits
RES0)
Always packed from 0 (lowest = 0)
Software error
(0)
0x14, SYN_ITS_OFF
Data was read from an ITS that is powered down.
0xF GICT_ERR0ADDR is populated
Software error
(0)
0x18, SYN_SPI_BLOCK.
Attempt to access an SPI block that is not
implemented.
0xE Block, bits[4:0]
Software error
(0)
0x19, SYN_SPI_OOR
Attempt to access a non-implemented SPI using (SET|
CLR)SPI.
0xE ID, bits[9:0]
Software error
(0)
0x1A, SYN_SPI_NO_DEST_TGT
An SPI has no legal target destinations.
0xF ID, bits[9:0]
Software error
(0)
0x1B, SYN_SPI_NO_DEST_1OFN
A 1 of N SPI cannot be delivered due to bad
GICR_CTLR.DPG<0|1NS|1S> or GICR_CLASSR
programming.
0xF ID, bits[9:0]
Software error
(0)
0x1C, SYN_COL_OOR
A collator message is received for a non-implemented
SPI, or is larger than the number of owned SPIs in a
multichip configuration.
0xF ID, bits[9:0]
Software error
(0)
0x1D, SYN_DEACT_IN
A Deactivate command to a nonexistent SPI, or with
incorrect groups set. Deactivate commands to LPI
and nonexistent PPI are not reported.
0xE None
Software error
(0)
0x1E, SYN_SPI_CHIP_OFFLINE
An attempt was made to send an SPI to an offline chip.
0xF ID, bits[9:0]
Software error
(0)
0x28, SYN_ITS_REG_SET_OOR
An attempt was made to set an Out Of Range (OOR)
interrupt. Only valid when GICR LPI injection registers
are supported.
0xE Core, bits[24:16]
Data, bits[15:0]
Software error
(0)
0x29, SYN_ITS_REG_CLR _OOR
An attempt was made to clear an OOR interrupt. Only
valid when GICR LPI injection registers are supported.
0xE Core, bits[24:16]
Data, bits[15:0]
Software error
(0)
0x2A, SYN_ITS_REG_INV_OOR
An attempt was made to invalidate an OOR interrupt.
Only valid when GICR LPI injection registers are
supported.
0xE Core, bits[24:16]
Data, bits[15:0]
Software error
(0)
0x2B, SYN_ITS_REG_SET_ENB
An attempt was made to set an interrupt when LPIs
are not enabled. Only valid when GICR LPI injection
registers are supported.
0xF Core, bits[24:16]
Data, bits[15:0]
Software error
(0)
0x2C, SYN_ITS_REG_CLR _ENB
An attempt was made to clear an interrupt when LPIs
are not enabled. Only valid when GICR LPI injection
registers are supported.
0xF Core, bits[24:16]
Data, bits[15:0]
Software error
(0)
0x2D, SYN_ITS_REG_INV_ENB
An attempt was made to invalidate an interrupt when
LPIs are not enabled. Only valid when GICR LPI
injection registers are supported.
0xF Core, bits[24:16]
Data, bits[15:0]
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