Infineon TriCore TC1.6P - Page 201

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-154
new_index = index + sign_ext(off10);
new_index = new_index < 0 ? new_index+length : new_index % length;
A[b+1] = {length[15:0], new_index[15:0]};
LD.BD[a], A[b], off10 (BO)(Post-increment Addressing Mode)
EA = A[b];
D[a] = sign_ext(M(EA, byte));
A[b] = EA + sign_ext(off10);
LD.BD[a], A[b], off10 (BO)(Pre-increment Addressing Mode)
EA = A[b] + sign_ext(off10);
D[a] = sign_ext(M(EA, byte));
A[b] = EA;
LD.BD[a], A[b], off16 (BOL)(Base + Long Offset Addressing Mode)
EA = A[b] + sign_ext(off16);
D[a] = sign_ext(M(EA, byte));
LD.BUD[a], off18 (ABS)(Absolute Addressing Mode)
EA = {off18[17:14], 14b'0, off18[13:0]};
D[a] = zero_ext(M(EA, byte));
LD.BUD[a], A[b], off10 (BO)(Base + Short Offset Addressing Mode)
EA = A[b] + sign_ext(off10);
D[a] = zero_ext(M(EA, byte));
LD.BUD[a], P[b] (BO)(Bit-reverse Addressing Mode)
31
off10[9:6]
28 27
00
H
22 21
off10[5:0]
16 15
b
12 11
a
8 7
09
H
0
31
off10[9:6]
28 27
10
H
22 21
off10[5:0]
16 15
b
12 11
a
8 7
09
H
0
31
off16[9:6]
28 27
off16[15:10]
22 21
off16[5:0]
16 15
b
12 11
a
8 7
79
H
0
31
off18[9:6]
28 27
01
H
26 25
off18[13:10]
22 21
off18[5:0]
16 15
off18[17:14]
12 11
a
8 7
05
H
0
31
off10[9:6]
28 27
21
H
22 21
off10[5:0]
16 15
b
12 11
a
8 7
09
H
0
31
-
28 27
01
H
22 21
-
16 15
b
12 11
a
8 7
29
H
0