Infineon TriCore TC1.6P - Page 202

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-155
index = zero_ext(A[b+1][15:0]);
incr = zero_ext(A[b+1][31:16]);
EA = A[b] + index;
D[a] = zero_ext(M(EA, byte));
new_index = reverse16(reverse16(index) + reverse16(incr));
A[b+1] = {incr[15:0], new_index[15:0]};
LD.BUD[a], P[b], off10 (BO)(Circular Addressing Mode)
index = zero_ext(A[b+1][15:0]);
length = zero_ext(A[b+1][31:16]);
EA = A[b] + index;
D[a] = zero_ext(M(EA, byte));
new_index = index + sign_ext(off10);
new_index = new_index < 0 ? new_index+length : new_index % length;
A[b+1] = {length[15:0], new_index[15:0]};
LD.BUD[a], A[b], off10 (BO)(Post-increment Addressing Mode)
EA = A[b];
D[a] = zero_ext(M(EA, byte));
A[b] = EA+sign_ext(off10);
LD.BUD[a], A[b], off10 (BO)(Pre-increment Addressing Mode)
EA = A[b] + sign_ext(off10);
D[a] = zero_ext(M(EA, byte));
A[b] = EA;
LD.BUD[a], A[b], off16 (BOL)(Base + Long Offset Addressing Mode)
EA = A[b] + sign_ext(off16);
D[a] = zero_ext(M(EA, byte));
LD.BUD[c], A[b] (SLR)
31
off10[9:6]
28 27
11
H
22 21
off10[5:0]
16 15
b
12 11
a
8 7
29
H
0
31
off10[9:6]
28 27
01
H
22 21
off10[5:0]
16 15
b
12 11
a
8 7
09
H
0
31
off10[9:6]
28 27
11
H
22 21
off10[5:0]
16 15
b
12 11
a
8 7
09
H
0
31
off16[9:6]
28 27
off16[15:10]
22 21
off16[5:0]
16 15
b
12 11
a
8 7
39
H
0