Infineon TriCore TC1.6P - Page 320

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-273
MULSD[c], D[a], const9 (RC)
(32 * K9) --> 32 signed saturated
result = D[a] * sign_ext(const9);
D[c] = ssov(result, 32);
MULSD[c], D[a], D[b] (RR2)
(32 * 32) --> 32 signed saturated
result = D[a] * D[b];
D[c] = ssov(result, 32);
Status Flags
Examples
mul d3, d1, d2
mul d2, d4, #21
H
mul e2, d5, d1
muls d2, d0, d0
result = D[a] * D[b];
D[a] = result[31:0];
C Not set by these instructions.
V 32-bit result:
overflow = (result > 7FFFFFFF
H
) OR (result < -80000000
H
);
if (overflow) then PSW.V = 1 else PSW.V = 0;
64-bit result:
It is mathematically impossible to generate an overflow when multiplying two 32-bit numbers and storing
the result in a 64-bit register.
SV if (overflow) then PSW.SV = 1 else PSW.SV = PSW.SV;
AV 32-bit result:
advanced_overflow = result[31] ^ result[30];
if (advanced_overflow) then PSW.AV = 1 else PSW.AV = 0;
64-bit result:
advanced_overflow = result[63] ^ result[62];
if (advanced_overflow) then PSW.AV = 1 else PSW.AV = 0;
SAV if (advanced_overflow) then PSW.SAV = 1 else PSW.SAV = PSW.SAV;
15
b
12 11
a
8 7
E2
H
0
31
c
28 27
05
H
21 20
const9
12 11
a
8 7
53
H
0
31
c
28 27
8A
H
16 15
b
12 11
a
8 7
73
H
0