Infineon TriCore TC1.6P User Manual

Infineon TriCore TC1.6P

484 pages

To Next Page

To Next Page

To Previous Page

To Previous Page

Page #321 background image

Loading...

Page #321 background image

TriCore

®

TC1.6P & TC1.6E

32-bit Unified Processor Core

Instruction Set

V1.0 2013-07

User Manual (Volume 2) 3-274

See Also

MUL.U, MADD, MSUB

mul d3, d11

Table of Contents

Table of Contents5
Preface6
- Bit Type Abbreviations7
- Text Conventions7
- Instruction Syntax8
- Operand Definitions8
- Instruction Mnemonic8
Instruction Set Information8
Implicit Operand Definitions9
Operation Modifiers9
16-Bit Opcode Formats10
Data Type Modifiers10
32-Bit Opcode Formats11
Opcode Field Definitions12
RTL Syntax13
Instruction Operation Syntax13
RTL Functions15
Cache RTL Functions16
Floating Point Operation Syntax18
Coprocessor Instructions20
List of os and I/O Privileged Instructions21
PSW Status Flags (User Status Bits)21
- Integer Arithmetic23
- Move23
- Addition and Subtraction23
Instruction Set Overview23
- Min, Max, Saturate/Conditional Arithmetic Instructions24
- Absolute Value, Absolute Difference24
- Division24
Multiply and Multiply-Add24
Count Leading Zeros, Ones and Signs25
Logical25
Bit-Field Extract and Insert26
Shift26
- Dextr27
- EXTR Operation27
- EXTR.U Operation27
- Insert28
- Packed Half-Word Data Format28
Packed Arithmetic28
- Packed Byte Data Format29
- DSP Arithmetic30
- PSW (Program Status Word) Status Flags and Arithmetic Instructions30
- Saturation30
- Usage30
- Guard Bits/Rounding31
- Overflow and Saturation31
- Sticky Advance Overflow and Block Scaling if FFT31
Special Case: -1 * -131
Packed Multiply and Packed MAC32
- Simple Compare33
- Accumulating Compare33
- Equivalent Comparison Operations33
Compare Instructions33
Packed Compare34
Compare with Shift34
- Simple Bit Operations35
- Shifting Bit Operations36
Accumulating Bit Operations36
Address Comparison37
Address Arithmetic37
- Unconditional Branch38
- LT.A Comparison Operation38
Branch Instructions38
- Conditional Jumps on Data Registers39
- Conditional Jumps on Address Registers39
Conditional Branch39
- Loop Instructions with Reduced Execution Overhead40
- Loop Instructions with Auto Incrementing/Decrementing Counter40
- Conditional Jumps on Bits40
Loop Instructions40
- Load/Store Basic Data Types41
- Addressing Modes41
Load and Store Instructions41
Store Bit and Bit Field42
Load Bit42
- Lower Context Saving and Restoring43
- Context Loading and Storing43
Context Related Instructions43
- System Call44
- Synchronization Primitives (DYSNC and ISYNC)44
System Instructions44
Access to the Core Special Function Registers (Csfrs)45
Enabling and Disabling the Interrupt System45
- Return (RET) and Return from Exception (RFE) Instructions46
- Trap Instructions46
- No-Operation (NOP)46
- Coprocessor (COP) Instructions/16-Bit Instructions46
- Instruction Set48
CPU Instructions48
- Abs49
- Absolute Value49
- ABS.B - Absolute Value Packed Byte50
- ABS.H - Absolute Value Packed Half-Word50
- ABSDIF - Absolute Value of Difference52
- ABSDIF.B - Absolute Value of Difference Packed Byte53
- ABSDIF.H - Absolute Value of Difference Packed Half-Word53
- ABSDIFS - Absolute Value of Difference with Saturation55
- ABSDIFS.H - Absolute Value of Difference Packed Half-Word W Saturation56
- ABSS - Absolute Value with Saturation57
- ABSS.H - Absolute Value Packed Half-Word with Saturation58
- Add59
- ADD.A - Add Address62
- ADD.B - Add Packed Byte63
- ADD.H - Add Packed Half-Word63
- ADDC - Add with Carry65
- ADDI - Add Immediate66
- ADDIH - Add Immediate High67
- ADDIH.A - Add Immediate High to Address68
- ADDS - Add Signed with Saturation69
- ADDS.H - Add Signed Packed Half-Word with Saturation71
- ADDS.HU - Add Unsigned Packed Half-Word with Saturation71
- ADDS.U - Add Unsigned with Saturation73
- ADDSC.A - Add Scaled Index to Address74
- ADDSC.AT - Add Bit-Scaled Index to Address74
- ADDX - Add Extended76
- AND - Bitwise and77
- AND.AND.T - Accumulating Bit Logical AND-AND79
- AND.ANDN.T - Accumulating Bit Logical AND-AND-Not79
- AND.NOR.T - Accumulating Bit Logical AND-NOR79
- AND.OR.T - Accumulating Bit Logical AND-OR79
- AND.EQ - Equal Accumulating81
- AND.GE.U - Greater than or Equal Accumulating Unsigned82
- AND.GE - Greater than or Equal Accumulating82
- AND.LT - Less than Accumulating84
- AND.LT.U - Less than Accumulating Unsigned84
- AND.NE - Not Equal Accumulating86
- AND.T - Bit Logical and87
- ANDN - Bitwise AND-Not88
- ANDN.T - Bit Logical AND-Not89
- BISR - Begin Interrupt Service Routine90
- BMERGE - Bit Merge92
- BSPLIT - Bit Split93
- CACHEA.I - Cache Address, Invalidate94
- CACHEA.W - Cache Address, Writeback96
- CACHEA.WI - Cache Address, Writeback and Invalidate98
- CACHEI.W - Cache Index, Writeback100
- CACHEI.I - Cache Index, Invalidate102
- CACHEI.WI - Cache Index, Writeback, Invalidate104
- CADD - Conditional Add106
- CADDN - Conditional Add-Not108
- Call110
- CALLA - Call Absolute112
- CALLI - Call Indirect113
- CLO - Count Leading Ones115
- CLO.H - Count Leading Ones in Packed Half-Words116
- CLS - Count Leading Signs117
- CLS.H - Count Leading Signs in Packed Half-Words118
- CLZ - Count Leading Zeros119
- CLZ.H - Count Leading Zeros in Packed Half-Words120
- CMOV (16-Bit) - Conditional Move (16-Bit)121
- CMOVN (16-Bit) - Conditional Move-Not (16-Bit)122
- CMPSWAP.W - Compare and Swap123
- Crc32125
- CSUB - Conditional Subtract126
- CSUBN - Conditional Subtract-Not127
- Debug128
- DEXTR - Extract from Double Register129
- DISABLE - Disable Interrupts130
- DSYNC - Synchronize Data131
- DVADJ - Divide-Adjust132
- DIV - Divide134
- DIV.U - Divide Unsigned134
- DVINIT.HU - Divide-Initialization Half-Word Unsigned136
- DVINIT - Divide-Initialization Word136
- DVINIT.H - Divide-Initialization Half-Word136
- DVINIT.B - Divide-Initialization Byte136
- DVSTEP - Divide-Step139
- DVSTEP.U - Divide-Step Unsigned139
- Enable Interrupts141
- EQ - Equal142
- EQ.A - Equal to Address144
- EQ.B - Equal Packed Byte145
- EQ.H - Equal Packed Half-Word145
- EQ.W - Equal Packed Word145
- EQANY.B - Equal any Byte147
- EQANY.H - Equal any Half-Word147
- EQZ.A - Equal Zero Address149
- EXTR - Extract Bit Field150
- EXTR.U - Extract Bit Field Unsigned150
- FCALL - Fast Call152
- FCALLA - Fast Call Absolute153
- FCALLI - Fast Call Indirect154
- FRET - Return from Fast Call155
- GE - Greater than or Equal156
- GE.U - Greater than or Equal Unsigned156
- GE.A - Greater than or Equal Address158
- IMASK - Insert Mask159
- INS.T - Insert Bit161
- INSN.T - Insert Bit-Not161
- INSERT - Insert Bit Field162
- ISYNC - Synchronize Instructions164
- IXMAX - Find Maximum Index165
- IXMAX.U - Find Maximum Index (Unsigned)165
- IXMIN - Find Minimum Index167
- IXMIN.U - Find Minimum Index (Unsigned)167
- J - Jump Unconditional169
- JA - Jump Unconditional Absolute170
- JEQ - Jump if Equal171
- JEQ.A - Jump if Equal Address173
- JGE - Jump if Greater than or Equal174
- JGE.U - Jump if Greater than or Equal Unsigned174
- JGEZ (16-Bit) - Jump if Greater than or Equal to Zero (16-Bit)176
- JGTZ (16-Bit) - Jump if Greater than Zero (16-Bit)177
- JI - Jump Indirect178
- JL - Jump and Link179
- JLA - Jump and Link Absolute180
- JLEZ (16-Bit) - Jump if Less than or Equal to Zero (16-Bit)181
- JLI - Jump and Link Indirect182
- JLT - Jump if Less than183
- JLT.U - Jump if Less than Unsigned183
- JLTZ (16-Bit) - Jump if Less than Zero (16-Bit)185
- JNE - Jump if Not Equal186
- JNE.A - Jump if Not Equal Address188
- JNED - Jump if Not Equal and Decrement189
- JNEI - Jump if Not Equal and Increment190
- JNZ (16-Bit) - Jump if Not Equal to Zero (16-Bit)191
- JNZ.A - Jump if Not Equal to Zero Address192
- JNZ.T - Jump if Not Equal to Zero Bit193
- JZ (16-Bit) - Jump if Zero (16-Bit)194
- JZ.A - Jump if Zero Address195
- JZ.T - Jump if Zero Bit196
- LD.A - Load Word to Address Register197
- LD.B - Load Byte200
- LD.BU - Load Byte Unsigned200
- LD.D - Load Double-Word204
- LD.DA - Load Double-Word to Address Register206
- LD.H - Load Half-Word208
- LD.HU - Load Half-Word Unsigned208
- LD.Q - Load Half-Word Signed Fraction212
- LD.W - Load Word214
- LDLCX - Load Lower Context217
- LDMST - Load-Modify-Store218
- LDUCX - Load Upper Context220
- LEA - Load Effective Address221
- Loop222
- LOOPU - Loop Unconditional223
- LT - Less than224
- LT.U - Less than Unsigned224
- LT.A - Less than Address226
- LT.B - Less than Packed Byte227
- LT.BU - Less than Packed Byte Unsigned227
- LT.H - Less than Packed Half-Word228
- LT.HU - Less than Packed Half-Word Unsigned228
- LT.WU - Less than Packed Word Unsigned229
- LT.W - Less than Packed Word229
- MADD - Multiply-Add230
- MADDS - Multiply-Add, Saturated230
- MADD.H - Packed Multiply-Add Q Format233
- MADDS.H - Packed Multiply-Add Q Format, Saturated233
- MADD.Q - Multiply-Add Q Format237
- MADDS.Q - Multiply-Add Q Format, Saturated237
- MADD.U - Multiply-Add Unsigned243
- MADDS.U - Multiply-Add Unsigned, Saturated243
- MADDM.H - Packed Multiply-Add Q Format Multi-Precision245
- MADDMS.H - Packed Multiply-Add Q Format Multi-Precision, Saturated245
- MADDR.H - Packed Multiply-Add Q Format with Rounding248
- MADDRS.H - Packed Multiply-Add Q Format with Rounding, Saturated248
- MADDR.Q - Multiply-Add Q Format with Rounding252
- MADDRS.Q - Multiply-Add Q Format with Rounding, Saturated252
- MADDSU.H - Packed Multiply-Add/Subtract Q Format254
- MADDSUS.H - Packed Multiply-Add/Subtract Q Format Saturated254
- MADDSUM.H - Packed Multiply-Add/Subtract Q Format Multi-Precision258
- Packed Multiply-Add/Subtract Q Format Multi-Precision Saturated258
- MADDSUR.H - Packed Multiply-Add/Subtract Q Format with Rounding261
- Packed Multiply-Add/Subtract Q Format with Rounding Saturated261
- MAX - Maximum Value265
- MAX.U - Maximum Value Unsigned265
- MAX.B - Maximum Value Packed Byte267
- MAX.BU - Maximum Value Packed Byte Unsigned267
- MAX.H - Maximum Value Packed Half-Word268
- MAX.HU - Maximum Value Packed Half-Word Unsigned268
- MFCR - Move from Core Register269
- MIN - Minimum Value270
- MIN.U - Minimum Value Unsigned270
- MIN.B - Minimum Value Packed Byte272
- MIN.BU - Minimum Value Packed Byte Unsigned272
- MIN.H - Minimum Value Packed Half-Word273
- MIN.HU - Minimum Value Packed Half-Word Unsigned273
- MOV - Move274
- MOV.A - Move Value to Address Register277
- MOV.AA - Move Address from Address Register278
- MOV.D - Move Address to Data Register279
- MOV.U - Move Unsigned280
- MOVH - Move High281
- MOVH.A - Move High to Address282
- MSUB - Multiply-Subtract283
- MSUBS - Multiply-Subtract, Saturated283
- MSUB.H - Packed Multiply-Subtract Q Format286
- MSUBS.H - Packed Multiply-Subtract Q Format, Saturated286
- MSUB.Q - Multiply-Subtract Q Format290
- MSUBS.Q - Multiply-Subtract Q Format, Saturated290
- MSUB.U - Multiply-Subtract Unsigned296
- MSUBS.U - Multiply-Subtract Unsigned, Saturated296
- MSUBAD.H - Packed Multiply-Subtract/Add Q Format298
- MSUBADS.H - Packed Multiply-Subtract/Add Q Format, Saturated298
- MSUBADM.H - Packed Multiply-Subtract/Add Q Format-Multi-Precision302
- Packed Multiply-Subtract/Add Q Format-Multi-Precision, Saturated302
- Packed Multiply-Subtract/Add Q Format with Rounding, Saturated305
- MSUBADR.H - Packed Multiply-Subtract/Add Q Format with Rounding305
- MSUBM.H - Packed Multiply-Subtract Q Format-Multi-Precision309
- Packed Multiply-Subtract Q Format-Multi-Precision, Saturated309
- MSUBR.H - Packed Multiply-Subtract Q Format with Rounding312
- MSUBRS.H - Packed Multiply-Subtract Q Format with Rounding, Saturated312
- MSUBR.Q - Multiply-Subtract Q Format with Rounding316
- MSUBRS.Q - Multiply-Subtract Q Format with Rounding, Saturated316
- MTCR - Move to Core Register318
- MUL - Multiply319
- MULS - Multiply, Saturated319
- MUL.H - Packed Multiply Q Format322
- MUL.Q - Multiply Q Format324
- MULS.U - Multiply Unsigned, Saturated327
- MUL.U - Multiply Unsigned327
- MULM.H - Packed Multiply Q Format-Multi-Precision329
- MULMS.H - MULMS.H (DEPRECATED) (Note: Deprecated in TC2!)331
- MULR.H - Packed Multiply Q Format with Rounding332
- MULR.Q - Multiply Q Format with Rounding334
- NAND - Bitwise NAND335
- NAND.T - Bit Logical NAND336
- NE - Not Equal337
- NE.A - Not Equal Address338
- NEZ.A - Not Equal Zero Address339
- NOP - no Operation340
- NOR - Bitwise nor341
- NOR.T - Bit Logical nor342
- NOT (16-Bit) - Bitwise Complement NOT (16-Bit)343
- OR - Bitwise or344
- OR.AND.T - Accumulating Bit Logical OR-AND346
- OR.ANDN.T - Accumulating Bit Logical OR-AND-Not346
- OR.NOR.T - Accumulating Bit Logical OR-NOR346
- OR.OR.T - Accumulating Bit Logical OR-OR346
- OR.EQ - Equal Accumulating348
- OR.GE - Greater than or Equal Accumulating349
- OR.GE.U - Greater than or Equal Accumulating Unsigned349
- OR.LT - Less than Accumulating351
- OR.LT.U - Less than Accumulating Unsigned351
- OR.NE - Not Equal Accumulating353
- OR.T - Bit Logical or354
- ORN - Bitwise OR-Not355
- ORN.T - Bit Logical OR-Not356
- Pack357
- Parity359
- Restore360
- RET - Return from Call361
- RFE - Return from Exception363
- RFM - Return from Monitor365
- RSLCX - Restore Lower Context366
- RSTV - Reset Overflow Bits367
- RSUB - Reverse-Subtract368
- RSUBS - Reverse-Subtract with Saturation369
- RSUBS.U - Reverse-Subtract Unsigned with Saturation369
- SAT.B - Saturate Byte370
- SAT.BU - Saturate Byte Unsigned371
- SAT.H - Saturate Half-Word372
- SAT.HU - Saturate Half-Word Unsigned373
- SEL - Select374
- SELN - Select-Not375
- SH - Shift376
- SH.EQ - Shift Equal378
- SH.GE - Shift Greater than or Equal379
- SH.GE.U - Shift Greater than or Equal Unsigned379
- SH.H - Shift Packed Half-Words381
- SH.LT - Shift Less than382
- SH.LT.U - Shift Less than Unsigned382
- SH.NE - Shift Not Equal384
- SH.XOR.T - Accumulating Shift-XOR385
- SH.XNOR.T - Accumulating Shift-XNOR385
- SH.NAND.T - Accumulating Shift-NAND385
- SH.AND.T - Accumulating Shift-AND385
- SHA - Arithmetic Shift387
- SHA.H - Arithmetic Shift Packed Half-Words389
- SHAS - Arithmetic Shift with Saturation391
- ST.A - Store Word from Address Register393
- ST.B - Store Byte396
- ST.D - Store Double-Word399
- ST.DA - Store Double-Word from Address Registers401
- ST.H - Store Half-Word403
- ST.Q - Store Half-Word Signed Fraction406
- ST.T - Store Bit408
- ST.W - Store Word409
- STLCX - Store Lower Context412
- STUCX - Store Upper Context413
- SUB - Subtract414
- SUB.A - Subtract Address416
- SUB.B - Subtract Packed Byte417
- SUB.H - Subtract Packed Half-Word417
- SUBC - Subtract with Carry419
- SUBS - Subtract Signed with Saturation420
- SUBS.U - Subtract Unsigned with Saturation420
- SUBS.H - Subtract Packed Half-Word with Saturation422
- SUBS.HU - Subtract Packed Half-Word Unsigned with Saturation422
- SUBX - Subtract Extended424
- SVLCX - Save Lower Context425
- SWAP.W - Swap with Data Register426
- SWAPMSK.W - Swap under Mask428
- SYSCALL - System Call430
- TRAPSV - Trap on Sticky Overflow431
- TRAPV - Trap on Overflow432
- UNPACK - Unpack Floating Point433
- Wait435
- XNOR - Bitwise XNOR436
- XNOR.T - Bit Logical XNOR437
- XOR - Bitwise XOR438
- XOR.EQ - Equal Accumulating439
- XOR.GE - Greater than or Equal Accumulating440
- XOR.GE.U - Greater than or Equal Accumulating Unsigned440
- XOR.LT.U - Less than Accumulating Unsigned442
- XOR.LT - Less than Accumulating442
- XOR.NE - Not Equal Accumulating444
- XOR.T - Bit Logical XOR445
- FPU Instructions446
- ADD.F - Add Float447
- CMP.F - Compare Float448
- DIV.F - Divide Float449
- FTOI - Float to Integer450
- FTOIZ - Float to Integer, Round Towards Zero451
- FTOQ31 - Float to Fraction452
- FTOQ31Z - Float to Fraction, Round Towards Zero453
- FTOU - Float to Unsigned454
- FTOUZ - Float to Unsigned, Round Towards Zero455
- ITOF - Integer to Float456
- MADD.F - Multiply Add Float457
- MSUB.F - Multiply Subtract Float459
- MUL.F - Multiply Float461
- Q31TOF - Fraction to Floating-Point462
- QSEED.F - Inverse Square Root Seed463
- SUB.F - Subtract Float464
- UPDFL - Update Flags465
- UTOF - Unsigned to Floating-Point466
LS and IP Instruction Summary Lists467
List of IP Instructions468
List of Instructions by Shortname474
List of Instructions by Longname478
Index482

Questions and Answers:

Need help?

Do you have a question about the Infineon TriCore TC1.6P and is the answer not in the manual?

Infineon TriCore TC1.6P Specifications

General

Brand	Infineon
Model	TriCore TC1.6P
Category	Microcontrollers
Language	English

Related product manuals

Infineon TriCore TC1.6E

Preview: Infineon XMC Series

Infineon XMC Series

Preview: Infineon XMC4700

Infineon XMC4700