RM0033 Rev 9 1365/1381
RM0033 Revision history
1375
05-Nov-2012
5
(continued)
I2C:
Modified Section 23.3.7: DMA requests.
Updated definition of PE and note related to SWRST bit, moved note
related to STOP bit to the whole register in Section 23.6.1: I
2
C
Control register 1 (I2C_CR1)
Updated bit 14 description in Section 23.6.3: I
2
C Own address
register 1 (I2C_OAR1).
CAN:
Updated dual CAN block diagram.
Updated register description and definition of CAN2SB bits in
Section : CAN filter master register (CAN_FMR).
ETHERNET:
RTPR renamed PM in Table 145: Source address filtering.
Updated value of HCLK for CR= 001 in Section : Ethernet MAC MII
address register (ETH_MACMIIAR).
USB OTG FS:
Updated remote wakeup signaling bit and the resume interrupt in
Section : Suspended state.
USB OTG HS:
Renamed PHYSEL into PHSEL and changed from bit 7 to bit 6 of the
OTG_HS_GUSBCFG register. Updated remote wakeup signaling bit
and the resume interrupt in Section : Suspended state
. Updated
OTG_HS_DIEPEACHMSK1and OTG_HS_DOEPEACHMSK1
address offsets and reset values.
FSMC:
Updated step b) in Section 31.3.1: Supported memories and
transactions.
Updated case of synchronous accesses in Section 31.5.4: NOR
Flash/PSRAM controller asynchronous transactions. Removed
caution note in Section 31.6.1: External memory interface signals.
Changed data_setup_phase and data_phase to DATAST in Section :
WAIT management in asynchronous accesses. Updated
Section 31.5.3: General timing rules/Signals synchronization.
Updated step3 of Section 31.6.4: NAND Flash operations, updated
Figure 418: Access to non ‘CE don’t care’ NAND-Flash and note
below. Updated access to I/O Space in Section 31.6.7: PC
Card/CompactFlash operations. Updated Table 202: 16-bit PC Card
and Table 204: 16-bit PC-Card signals and access type.
Updated BUSTURN bit definition in Section : SRAM/NOR-Flash
chip-select control registers 1..4 (FSMC_BCR1..4). Changed bits 16
to 19 to BUSTURN in Section : SRAM/NOR-Flash chip-select timing
registers 1..4 (FSMC_BTR1..4).
Changed min. value for address set to 0 in Table 175, Ta bl e 17 7,
Table 178, Table 180, and Table 181.
Table 224. Document revision history (continued)
Date Version Changes
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