Revision history RM0033
1366/1381 RM0033 Rev 9
05-Nov-2012
5
(continued)
Debug:
Updated IO states after reset in Section 32.4.3: Internal pull-up and
pull-down on JTAG pins.Updated REV_ID in Section 32.6.1: MCU
device ID code.
Electronic signature:
Updated Section 33: Device electronic signature introduction as well
as Section 33.2: Flash size.
16-Sep-2013 6
PWR:
Updated Section 4.2.2: Brownout reset (BOR).
Replaced “The backup domain includes 4 Kbytes of backup SRAM
accessible only from the CPU” with “The backup domain includes 4
Kbytes of backup SRAM” in Backup SRAM.
Updated Table 10: Stop mode.
Updated description of “Bit 0 WUF: Wakeup flag” in PWR_CSR
register.
RCC
Modified description of PLLN bits in Section 5.3.2: RCC PLL
configuration register (RCC_PLLCFGR).
GPIO:
Removed frequency value in description of OSPEEDR bits.
Interrupts:
Updated Section 8.1.1: NVIC features.
DAC:
Updated Section 10.9.3: Interleaved mode, Section 10.9.4: Alternate
trigger mode, and Section 10.9.6: Combined regular simultaneous +
alternate trigger mode to describe case of interrupted conversion.
RTC:
Removed “or when the Flash readout protection is disabled” in
Section 22.6.14: RTC backup registers (RTC_BKPxR).
Replaced all occurrences of “power-on reset” with “backup domain
reset”.
Replaced "System reset: 0x0000 0000 when BYPSHAD = 0. Not
affected when BYPSHAD = 1." with "System reset: 0x0000 0000
before the RSF flag is set, then the correct value is available in
Section 22.6.1: RTC time register (RTC_TR).
Replaced "System reset: 0x0000 2101 when BYPSHAD = 0. Not
affected when BYPSHAD = 1." with "System reset: 0x0000 2101
before the RSF flag is set, then the correct value is available in
Section 22.6.2: RTC date register (RTC_DR).
Added under Table 80: RTC register map and reset values.
Table 224. Document revision history (continued)
Date Version Changes
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