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ST STM32F207 series User Manual

ST STM32F207 series
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RM0033 Rev 9 1373/1381
RM0033 Revision history
1375
26-Apr-2018
8
(continued)
USB OTG_HS (continued)
Changed PTXFSAVL access type to ‘r’ in Section : OTG_HS host
frame number/frame time remaining register (OTG_HS_HFNUM)
Renamed bit 2 name into AHBERRM and definition updated in
Section : OTG_HS host channel-x interrupt mask register
(OTG_HS_HCINTMSKx) (x = 0..11, where x = Channel_number).
Updated bit 7:9 definition in Section : OTG_HS device control
register (OTG_HS_DCTL).
Added NAKM and AHBERRM bits in Section : OTG_HS device IN
endpoint common interrupt mask register (OTG_HS_DIEPMSK).
Added NYETMSK, NAKMSK, BERRM, STSPHSRXM and
AHBERRM bits in Section : OTG_HS device OUT endpoint common
interrupt mask register (OTG_HS_DOEPMSK).
Replaced DWORDS by words in Section : OTG_HS Device
threshold control register (OTG_HS_DTHRCTL).
Added AHBERRM in Section : OTG_HS device each in endpoint-1
interrupt register (OTG_HS_DIEPEACHMSK1).
Updated STALL bit definition in Section : OTG_HS device endpoint-x
control register (OTG_HS_DOEPCTLx) (x = 1..5, where x =
Endpoint_number).
Removed BERR bit and added BNA, INEPNM and AHBERR bits in
Section : OTG_HS device endpoint-x interrupt register
(OTG_HS_DIEPINTx) (x = 0..5, where x = Endpoint_number).
Added NAK, BERR, OUTPKTERR and AHBERR bits in Section :
OTG_HS device endpoint-x interrupt register (OTG_HS_DOEPINTx)
(x = 0..5, where x = Endpoint_number).
FSMC
Updated Section 31.3: AHB interface.
Modified Figure 411: Multiplexed write accesses.
Added note related to the hold phase delay below Figure 417:
NAND/PC Card controller timing for common memory access.
Updated Section 31.6.5: NAND Flash prewait functionality.
Updated note related to IRS and IFS bits in FSMC_SR.
Updated BUSTURN bitfield description in SRAM/NOR-Flash write
timing registers 1..4 (FSMC_BWTR1..4) and SRAM/NOR-Flash
chip-select timing registers 1..4 (FSMC_BTR1..4).
Updated MEMHOLDx in Common memory space timing register 2..4
(FSMC_PMEM2..4) and ATTHOLD in Attribute memory space timing
registers 2..4 (FSMC_PATT2..4).
DEBUG
Updated REV_ID in DBGMCU_IDCODE register.
Table 224. Document revision history (continued)
Date Version Changes

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ST STM32F207 series Specifications

General IconGeneral
BrandST
ModelSTM32F207 series
CategoryMicrocontrollers
LanguageEnglish

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