An event is represented by a condition register bit changing from a 1 to 0 or 0 to 1. When an event
occurs and the appropriate NTR or PTR bit is set, the corresponding event register bit is set to 1. The
event bit remains latched to 1 until the event register is read or the status model is reset. When an
event register bit is set and its corresponding enable bit is set, the summary bit of the register is set
to 1. This, in turn, sets a bit in a higher-level condition register, potentially cascading to the associated
summary bit of the Status Byte Register.
Queues
The 2600B uses queues to store messages. The queues include:
• Command queue: Holds commands that are available for execution.
• Output queue: Holds response messages.
• Error queue: Holds error and status messages.
When a queue contains data, it sets the condition bit for that queue in one of the registers. The
condition bits are:
• Command queue: CAV in the Operation Status Remote Summary Register
• Output queue: MAV in the Status Byte Register
• Error queue: EAV in the Status Byte Register
The CAV, MAV, and EAV bits in the registers are cleared when the queue is empty. Queues
empty when:
• Commands are executed
• Errors are read from the error queue
• Response messages are read from the instrument
All 2600B queues are first-in, first-out (FIFO).
The Status model diagrams (on page 12-5) shows how the queues are structured with the
other registers.
Command queue
The command queue holds commands that have been received from a remote interface that are
available for execution. This allows the 2600B to accept multiple commands and queue them for
execution.
When a command is received from a remote interface, the command available (CAV) bit in the
Operation Status Remote Summary Register is set. For additional detail, see
status.operation.remote.* (on page 9-325).
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