Status Byte Register
The summary messages from the status registers and queues are used to set or clear the appropriate
bits (B0, B1, B2, B3, B4, B5, and B7) of the Status Byte Register. These summary bits do not latch,
and their states (0 or 1) are dependent upon the summary messages (0 or 1). For example, if the
Standard Event Register is read, its register is cleared. As a result, its summary message resets to 0,
which then resets the ESB bit in the Status Byte Register.
The Status Byte Register also receives summary bits from itself, which sets the Master Summary
Status, or MSS, bit.
Figure 145: Status byte and service request (SRQ)