Control, Transmission, and Synchronization Interfaces
5-16 Issue 8.0 July 2002
accommodated. In the holdover mode, the on-board oscillator frequency will not
degrade below the stratum 3 level.
The TG3 (DS1) circuit packs distribute 155.52 MHz timing signals to the low
speed interface circuit packs on the Low Speed Shelf - System Controller and the
OC48 TRMTR circuit packs on the Enhanced High Speed Shelf (or High Speed
Shelf).
In the loop timed mode, the TG3 (DS1) circuit packs can also provide DS1
synchronization outputs to the office BITS clock or other central office equipment.
The LAA17 TG3 (DS1) circuit pack derives the DS1 synchronization outputs from
the internal oscillator. The LAA18 TG3 (DS1) circuit pack derives the DS1
synchronization outputs directly from the OC-48 line reference signal. If the
OC-48 line reference signals fail, the TG3 (DS1) circuit pack transmits DS1 alarm
indication signals (AIS) to the BITS clock to prevent any uncontrolled timing loops.
The DS1 reference input interface (TIMING IN PRI and TIMING IN SECY) and the
DS1 reference output interface (TIMING OUT 1 and TIMING OUT 2) are located
on the interconnection panel of the Low Speed Shelf - System Controller. For
more information about the physical location of the DS1 reference interfaces, refer
to Volume I, Section 3, "Platform Descriptions."
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