Circuit Pack Descriptions
Issue 8.0 July 2002
7-101
A switching matrix interfaces with up to three 155.52 Mb/s buses (add/drop, high
speed protection, and through) that carry up to eighteen 155.52 Mb/s signals each
(sixteen service and two protection). The add/drop bus allows access to the low
speed interface circuit packs for local traffic to be added. The high speed
protection bus allows the through traffic from the OC48 RCVR (A/D) circuit pack to
be looped back to the OC48 TRMTR (A/D) circuit pack. The through bus allows
through traffic to be routed from OC-48 high speed line 1E to 1W or from OC-48
high speed line 1W to 1E. The switching matrix routes sixteen 155.52 Mb/s
signals to the timing recovery circuit. The timing recovery circuit extracts a 155.52
MHz timing signal from the data stream, retimes the data with respect to the
output clock, and passes it to the pointer processor.
Figure 7-31. OC48 TRMTR A/D Circuit Pack (739B5, 739C5,
739E[1-16], 739G[1-8], 739H[1-16], 739J5, 739P5, 739R5,
and 739S5) Block Diagram
155 Mb/s
PLL
Signals
SONET Overhead
BCLAN
OC-48
-48 V (A)
-48 V (B)
155.52 MHz
Timing
Electrical
To
Optical
Module
Byte
Multiplexer
Transmit
Byte
Processor
Pointer
Processor
Timing
Recovery
Switching
Matrix
Timing
Interface
Board
Controller
Circuit
Power
Circuit
STS-1
Time
Slot
Assignment
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