Control, Transmission, and Synchronization Interfaces
Issue 8.0 July 2002
5-41
Figure 5-27. Example of a Timing Loop Resulting from Inconsistent DS1
Timing Interfaces
FT-2000
FT-2000
FT-2000
FT-2000
BITS
DS3/EC-1/OC-3
DS3/EC-1/OC-3
BITS
Independent
Clock
BITS
S
P
Externally Timed
S
P
Externally Timed
S
P = TIMING IN PRI to TG3-1
S = TIMING IN SECY to TG3-2
1 = TIMING OUT 1 from TG3-1
2 = TIMING OUT 2 from TG3-2
Externally
Timed
Externally
Timed
P
1
1
BITS
2
P
S
DS3/EC-1/OC-3