Circuit Pack Descriptions
7-36 Issue 8.0 July 2002
General Description of Operation 7
The DS3 circuit pack terminates three bidirectional DS3 lines complying with
standard DSX-3 signal specifications. The three DS3 signals are multiplexed to
one 155.52 Mb/s signal and sent to the OC48 Transmitter (OC48 TRMTR) circuit
pack. In the receive direction, the DS3 circuit pack accepts one 155.52 Mb/s
signal from an OC48 Receiver (OC48 RCVR) circuit pack and demultiplexes it to
three DS3 signals. The DS3 circuit pack also interfaces with the Line Controller
(LNCTL) circuit pack for that particular OC-48 high speed line.
Detailed Description of Operation 7
Transmission Circuitry 7
Transmit Direction. 7Figure 7-14 provides an overall block diagram of the DS3
circuit pack.
Figure 7-14. DS3 Circuit Pack Block Diagram
DS3
DS3
HS
(OUT)
DS3/STS-1
From DSX-3
From LSSW
Input
Protection
Intfc
Output
Protection
Intfc
Power
Circuit
Board
Controller
Circuit
Receiver
Driver
Sync/
Desync
Receive Direction
Byte
Timing
Intfc
Intfc
TRMTRs
To OC48
From OC48
Transmit Direction
To DSX-3
To LSSW (IN)
From TG3
(DS1)
Mux/
Demux
BCLAN
-48V (B)
-48V (A)
RCVRs
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