Maintenance Description
Issue 8.0 July 2002
9-75
For the local test, the output of the OC48 TRMTR circuit pack must be
looped back with a single-mode fiber jumper and a lightguide buildout to
the input of the OC48 RCVR circuit pack on the line(s) to be tested. For
example, when all lines are being tested, all OC48 TRMTR and OC48
RCVR circuit pack pairs must be manually looped back.
The FT-2000 OC-48 Add/Drop-Rings Terminal performs the following tests:
— To verify the continuity of each add/drop transmission path, each
DS3 circuit pack inserts one parity bit error on each DS3 signal
toward each high-speed line. The output of the OC48 TRMTR circuit
pack is looped back to the OC48 RCVR circuit pack and the DS3
circuit pack monitors each DS3 signal from the high-speed line. If
only one parity bit error is detected within 1 second, the test passes.
Rather than checking parity, the STS1E and OC3/OC12 (1.3 STD)
circuit packs use special test signals with a known content to verify
the continuity of add/drop transmission path.
— To verify the parity error rate of each add/drop transmission path,
each DS3 circuit pack monitors each DS3 signal from the
high-speed line for errors over a 4-second period. If no errors are
detected in the 4-second period, the test passes.
— To verify the continuity of each through transmission path, the east
OC48 RCVR circuit pack inserts one parity bit error on each STS-3
tributary toward the west OC48 TRMTR circuit pack. The west
OC48 RCVR circuit pack also inserts one parity bit error on each
STS-3 tributary toward the east OC48 TRMTR circuit pack. The
OC48 TRMTR circuit packs monitor each STS-3 tributary. If only
one parity bit error is detected within 1 second, the test passes.
— To verify the parity error rate of each through transmission path,
each OC48 TRMTR circuit pack monitors each STS-3 tributary
(from the OC48 RCVR circuit pack of the other high-speed line) for
errors over a 4-second period. If no errors are detected in the
4-second period, the test passes.
— To verify the continuity of each loopback transmission path, the east
OC48 RCVR circuit pack inserts one parity bit error on each STS-3
tributary toward the east OC48 TRMTR circuit pack. The west OC48
RCVR circuit pack also inserts one parity bit error on each STS-3
tributary toward the west OC48 TRMTR circuit pack. The OC48
TRMTR circuit packs monitor each STS-3 tributary. If only one parity
bit error is detected within 1 second, the test passes.
— To verify the parity error rate of each loopback transmission path,
each OC48 TRMTR circuit pack monitors each STS-3 tributary
(from the OC48 RCVR circuit pack of the same high-speed line) for
errors over a 4-second period. If no errors are detected in the
4-second period, the test passes.
To Next Page
Loading...
Need help?
General