Maintenance Description
9-66 Issue 8.0 July 2002
Figure 9-22. TG3 (DS1) Circuit Pack Protection (FT-2000 OC-48
Add/Drop-Rings Terminal)
The number 1 TG3 (DS1) circuit pack on the Low Speed Shelf - System Controller
provides the following:
â– Primary timing to the STS1E, IS3, OC3 (1.3 STD) and OC12 (1.3 STD)
circuit packs that terminate add/drop traffic to/from the OC-48 high-speed
line 1W and the DS3 circuit packs that terminate add/drop traffic to/from the
OC-48 high-speed line 1E
â– Primary timing to the east OC48 TRMTR circuit pack on the Enhanced
High Speed Shelf (or high-speed Shelf)
â– Secondary timing to the STS1E, IS3, OC3 (1.3 STD) and OC12 circuit
packs that terminate add/drop traffic to/from the OC-48 high-speed line 1E
and the DS3 circuit packs that terminate add/drop traffic to/from the OC-48
high-speed line 1W
â– Secondary timing to the west OC48 TRMTR circuit pack on the Enhanced
High Speed Shelf (or high-speed Shelf)
Low
Speed
West
Low
Speed
East
155.52 MHz
25.92 MHz
Low Speed Shelf
System Controller
DS1 Reference
DS1 Reference
DS1 Reference
DS1 Reference
TG3 1 TG3 2
nc-ft2000-035
OC-48 Reference OC-48 Reference
Enhanced
High Speed Shelf
OC48 RCVR OC48 TRMTR OC48 RCVR OC48 TRMTR
(W) (E) (E)(W)
Primary
Secondary