Maintenance Description
Issue 8.0 July 2002
9-67
■ An internal synchronization signal to the number 2 TG3 (DS1) on the Low
Speed Shelf - System Controller.
The number 2 TG3 (DS1) circuit pack on the Low Speed Shelf - System Controller
provides the following:
■ Primary timing to the STS1E, IS3, OC3 (1.3 STD) and OC12 (1.3 STD)
circuit packs that terminate add/drop traffic to/from the OC-48 high-speed
line 1E and the DS3 circuit packs that terminate add/drop traffic to/from the
OC-48 high-speed line 1W
■ Primary timing to the west OC48 TRMTR circuit pack on the Enhanced
High Speed Shelf (or High Speed Shelf)
■ Secondary timing to the STS1E, IS3, OC3 (1.3 STD) and OC12 (1.3 STD)
circuit packs that terminate add/drop traffic to/from the OC-48 high-speed
line 1W and the DS3 circuit packs that terminate add/drop traffic to/from the
OC-48 high-speed line 1E
■ Secondary timing to the east OC48 TRMTR circuit pack on the Enhanced
High Speed Shelf (or High Speed Shelf)
■ An internal synchronization signal to the number 1 TG3 (DS1) on the Low
Speed Shelf - System Controller.
If the number 1 TG3 (DS1) circuit pack fails, the number 2 TG3 (DS1) circuit pack
will provide timing for the transmit circuits. Conversely, if the number 2 TG3 (DS1)
circuit pack fails, the number 1 TG3 (DS1) circuit pack will provide timing.
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