Control, Transmission, and Synchronization Interfaces
Issue 8.0 July 2002
5-15
Loop Timed Mode—only for Point-to-Point
Releases of FT-2000 5
In the loop timed mode (Figure 5-8), the TG3 (DS1) circuit packs on the Low
Speed Shelf - System Controller derive timing from the incoming OC-48 signals.
The TG3 (DS1) circuit packs accept an OC-48 line reference signal (25.92 MHz)
from the OC48 RCVR circuit packs and derive the internal synchronization used
by the transmission packs.
Figure 5-8. Loop Timed Synchronization
The OC-48 line reference signals are continuously monitored for error-free
operation. If the primary OC-48 line reference signal becomes corrupted, the TG3
(DS1) circuit pack will select the secondary OC-48 line reference signal without
causing service degradations. If both OC-48 line reference signals are corrupted,
the digital phase-locked loop (DPLL) circuit will attempt to lock on to the primary
DS1 synchronization input (if equipped). If the primary DS1 synchronization input
is not equipped or fails, the DPLL circuit will attempt to lock on to the secondary
DS1 synchronization input (if equipped). If all these references fail, the DPLL
circuit holds the on-board oscillator frequency at the last good reference sample
while the references are repaired (holdover mode). This mechanism is provided
so that operation with or without an external BITS clock can be easily
1
2
TG3
TRMTR
1
2
TG3
S
P
S
P
RCVR
155.52 MHz
25.92 MHz
155.52 MHz
155.52 MHz25.92 MHz
Complementary
(Optional)
System Controller
OC48 OC48
Low Speed
Interfaces
Low Speed
Interfaces
Low Speed Shelf -
Low Speed Shelf -
Enhanced
DS1 Outputs
High Speed Shelf
(or High Speed Shelf)
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