Control, Transmission, and Synchronization Interfaces
Issue 8.0 July 2002
5-17
Externally Timed Mode 5
In the externally timed mode (phase locked mode in releases prior to Release 5)
(Figure 5-9), each TG3 (DS1) circuit pack accepts a DS1 synchronization
reference signal from an external stratum 3 or better clock. In bidirectional 2-fiber
ring applications, the DS1 references synchronize the local FT-2000 OC-48
Add/Drop-Rings Terminal, and other FT-2000 OC-48 Add/Drop-Rings Terminals
that are through timed, with other network equipment operating under the same
primary clock source. Within the TG3 (DS1) circuit pack, a highly stable DPLL
circuit removes any transient impairments on the DS1 reference for improved jitter
performance.
Figure 5-9. Externally Timed Synchronization
The DS1 references are continuously monitored. If the primary DS1 reference
becomes corrupted, the TG3 (DS1) circuit pack will select the secondary DS1
reference without causing service degradations. If both DS1 references are
corrupted, the DPLL circuit holds the on-board oscillator frequency at the last
good reference sample while the DS1 references are repaired (holdover mode). In
the holdover mode, the on-board oscillator frequency will not degrade below the
stratum 3 level.
The TG3 (DS1) circuit packs distribute 155.52 MHz timing signals to the low
speed interface circuit packs on the Low Speed Shelf - System Controller and the
OC48 TRMTR circuit packs on the Enhanced High Speed Shelf (or High Speed
Shelf).
TRMTR
TG3-2
155.52 MHz
OC48
Low Speed
Interfaces
System Controller
Low Speed Shelf -
Enhanced/Condensed
High Speed Shelf
(or High Speed Shelf)
TG3-1
DS1 Output
155.52 MHz
Low Speed
Interfaces
DS1 Inputs
Synchronized
Reference
(Stratum 3 or
Better)
DS1 Output
1W
1E
TRMTR
OC-48
155.52
MHz
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