Maintenance Description
Issue 8.0 July 2002
9-69
Figure 9-23. DS1 Reference Protection
OC-48 Line Reference Protection 9
FT-2000 OC-48 Add/Drop-Rings Terminal . 9When the FT-2000 OC-48
Add/Drop-Rings Terminal is provisioned for the through timed mode, the TG3
(DS1) circuit packs on the Low Speed Shelf - System Controller derive timing from
two 25.92 MHz reference signals obtained from the incoming OC-48 signals as
shown in Figure 9-24.
The west OC48 RCVR circuit pack recovers the 2.5 GHz clock signal from the
incoming OC-48 signal on OC-48 high-speed line 1W and generates the primary
25.92 MHz reference signal for the number 1 TG3 (DS1) circuit pack. The east
OC48 RCVR circuit pack recovers the 2.5 GHz clock signal from the incoming
OC-48 signal on OC-48 high-speed line 1E and generates the primary 25.92 MHz
reference signal for the number 2 TG3 (DS1) circuit pack.
If an OC-48 line reference signal or the OC-48 high-speed line fails, the TG3
(DS1) circuit pack switches to the secondary OC-48 line reference signal. If both
OC-48 line reference signals fail, the TG3 (DS1) circuit pack holds the on-board
oscillator frequency at the last good reference sample (holdover mode). In the
holdover mode, the on-board oscillator frequency will not degrade below the
stratum 3 level.
TG3 (1) TG3 (2)
25.92 MHz
25.92 MHz
~~
Transmit
Circuits
Transmit
Circuits
Primary
(DS1) (DS1)
Secondary
TIMING IN PRI
1.544 MHz
TIMING IN SECY
1.544 MHz
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