Circuit Pack Descriptions
7-90 Issue 8.0 July 2002
The receive byte processor then frames on the incoming signals. The signals are
descrambled and tested for section (B1) and line (B2) parity errors. The error
rates are compared to user-settable thresholds. The SONET transport overhead
bytes are also extracted and sent to the optional OHCTL (TERM) circuit pack. The
receive byte processor also tests overhead parity and inserts overhead alarm
indication signals (AIS). The status of the K1 and K2 bytes (used for protection
switching) is also monitored. A timing signal (25.92 MHz) is derived from the 2.5
GHz clock signal and sent to the Timing Generator, Stratum 3 - DS1 [TG3 (DS1)]
circuit packs.
Figure 7-28. OC48 RCVR A/D (839B5 and 839E5) Circuit Pack Block
Diagram
155 Mb/s
Signals
SONET Overhead
BCLAN
OC-48
25.92 MHz Timing
Receive
Byte
Processor
Byte
Demux
Optical
To
Electrical
Module
Board
Controller
Circuit
Power
Circuit
-48 V (A)
-48 V (B)
A
B
C
STS-1
Time Slot
Assignment
STS-1
Time Slot
Assignment
155 Mb/s
Signals
A
B
C
To Next Page
Loading...
Need help?
General