Circuit Pack Descriptions
Issue 8.0 July 2002
7-91
The 839B2, 839B4B, and 839E5 OC48 RCVR A/D circuit packs scramble the
155.52 Mb/s signals and pass them through a switching matrix to the low speed
interface circuit packs. The switch matrix is used for implementing protection
access, high speed protection, and low speed protection.
The receive byte processor (RBP) of the 839B5 OC48 RCVR A/D circuit pack
transmits the sixteen 155.52 Mb/s signals to two STS-1 time slot assignment
(TSA) devices that together form an equivalent 48x162 STS-1 crosspoint switch.
Each STS-1 TSA device has 32 STS-3 inputs and 32 STS-3 outputs. The 16
155.52 Mb/s signal (STS-3) outputs from the receive byte processor are
connected to the input of both STS-1 TSA devices (the other 16 inputs per device
are unused). Fifty-four of the 64 total STS-3 output channels from the two devices
are connected to the backplane.
Within the STS-1 TSA devices, the 16 STS-3 input channels are demultiplexed
into 48 STS-1 tributaries. Each of these 48 inputs can be assigned to any of the
162 STS-1 time slots available in the 54 STS-3 output signals from the two
devices. The STS-1 inputs can be broadcast to several or all outputs but do not
have to be connected to any output. The 162 STS-1 signals are multiplexed back
into 54 STS-3 signals after time slot assignment.
The connection matrix of the STS-1 TSA devices is programmed by the Board
Controller. The switch fabric provisioning is fully data hitless and 100 percent
non-blocking.
The STS-3 inputs to the STS-1 TSA devices are arranged in groups of four, or
“quads.”
The outgoing STS-3 tributaries are arranged in three groups (A, B, and C), each
containing sixteen service STS-3 tributaries and two protection STS-3 tributaries.
A low speed protection switch can be performed by switching input signals to
output protection tributaries.
The OC48 RCVR A/D circuit pack interfaces with up to three different buses
(add/drop, high speed protection, and through) that carry up to eighteen 155.52
Mb/s signals each (sixteen service and two protection). The add/drop bus
provides access to the low speed interface circuit packs. The high speed
protection bus provides access to the OC48 TRMTR A/D circuit pack in the same
direction for high speed line protection switching. The through bus provides
access to the OC48 TRMTR A/D circuit pack for the 155.52 Mb/s signals that are
passed through in bidirectional ring applications.
To Next Page
Loading...