Circuit Pack Descriptions
7-74 Issue 8.0 July 2002
Transmit Direction. 7In the transmit direction, the circuit pack accepts one
OC-12/12C optical signal. This optical input is connected to an optical receiver
module which converts the optical OC-12/12C signal into electrical 522.08 MB/s
STS-12/12C data and recovered clock signals. The STS-12/12C clock and data
signals are connected to the 1:4 DEMUX section of the STS12 MUX/DEMUX
device which de-multiplexes the STS-12/12C signal into four STS-3 bit streams
and a common clock. The four bit streams and clock are connected to the
STM4RBP (receive byte processor) which re-assembles the four bit streams into
four STS-3 rate data signals and processes the received OC-12/12C line
overhead bytes. The outputs from the receive byte processor are the four STS-3
rate data signals, a common clock, a common sync signal and the received line
hyper channel data and clock signals. In addition tot he data inputs, the receive
byte processor receives a loss of signal control flag from the receiver module
which can be used for automatic line/section AIS and FERF insertion.
Following the receive byte processor, the transmit STS12PP (pointer processor)
performs frequency adjustments and pointer processing on the four received
STS-3 rate clock and data signals that synchronizes the STS-3 rate data to the
155.52 MHz system clock. The transmit pointer processor also receives an AIS
control input from the receive byte processor which can be used for automatic
path AIS insertion when there is a loss of frame, loss of clock, or a loss or
received STS-3 rate data to the receive byte processor. The outputs of the
transmit pointer processor are connected to the HS switch matrix which
distributes them to the backplane.
Receive Direction. 7In the receive direction, four electrical inputs from each of the
LS slots are connected to the switch matrix which selects one of the STS-3 rate
inputs for each of the four receive input STS-3 rate signals. The four selected
STS-3 rate input data signals are connected to four timing recovery circuits which
recover a 155.52 MHz clock signal for each of the received data signals and
re-times each data signal with its recovered clock.
Following the timing recovery circuits, the receive pointer processor performs
frequency adjustment and pointer processing on the four STS-3 rate data signals
to synchronize the STS-3 rate data to the 155.52 MHz system clock. The outputs
of the receive pointer processor are connected to the STM4TBP (transmit byte
processor) which byte processes the four STS-3 rate signals, adds the transmit
OC-12/12C line overhead bytes, and generates four STS-3 rate bit streams for bit
interleaving into an OC-12/12C signal. The four bit stream outputs are connected
to the 4:1 mux section of the STS12 MUX/DEMUX device which bit interleave
multiplexes the four bit streams into an STS12/12C data signal. Included in the
STS12 MUX device is a 622.08 MHz PLL synthesizer which generates an STS-12
clock which is synchronized with the 155.52 MHz system clock. The STS-12/12C
data signal is then connected to the laser module.
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