Circuit Pack Descriptions
Issue 8.0 July 2002
7-75
Control Circuitry 7
The board controller circuit controls all the circuit pack activities. The board
controller circuit interfaces with the LNCTL circuit pack using the board controller
local area network (BCLAN). The OC12 (1.3 STD) circuit pack reports the status
of the circuit pack and the incoming OC-12 and STS-3/3c signals, as well as the
circuit pack inventory information (CLEI code, serial number, etc.). The LNCTL
circuit pack uses the status information for fault detection and isolation. The OC12
(1.3 STD) circuit pack also responds to control signals from the LNCTL circuit
pack.
Overhead Controller Circuitry 7
The transport overhead hyperchannel (TOH) circuitry provides access to the data
communications channel (DCC) of the OC-12 line. Access is only provided to the
D1-D3 overhead bytes of the DCC.
Timing Circuitry 7
The OC12 (1.3 STD) circuit pack accepts one 155.52 MHz clock signal from each
of the two Timing Generator, Stratum 3 - DS1 [TG3 (DS1)] circuit packs (primary
and secondary). During normal operation, the timing interface circuitry selects the
clock signal that is used and automatically switches to the other clock signal if it
detects a loss of signal. The board controller can also override the automatic clock
selection mode and force either clock signal to be selected.
When the network element is in the through-timed mode, the OC-12 Timing
Direction parameter determines the high-speed line (1W or 1E) from which the
OC-12 derives its timing. The OC-12 Timing Direction parameter is
user-provisionable via the CIT, and its default value is 1W. This parameter may be
needed when the OC-12 is used to distribute timing to far-end equipment. When
the network element is not through-timed, the OC-12 derives its timing from that
element system clock.
Protection Circuitry 7
Low-Speed Interface Protection. 7Optional 1+1 non-revertive OC12 (1.3 STD)
circuit pack protection in the transmit (toward the OC-48 line) and/or receive
(toward the OC-12 line) direction is provided. For 1+1 non-revertive protection,
two OC12 (1.3 STD) circuit packs must be placed in adjacent low-speed interface
slots of the Low Speed Shelf - System Controller (for example, LS INTFC slots
1A-2B and 3A-4B or 5A-6A and 7A-8B). Both OC12 (1.3 STD) circuit packs
transmit the same OC-12 signal toward the lightguide cross-connect panel (or
equivalent). Both OC12 (1.3 STD) circuit packs receive the same OC-12 signal
from the lightguide cross-connect panel (or equivalent) and transmit STS-3/3c
signals to the OC48 TRMTR circuit pack(s). The OC12 circuit packs continuously
monitor the incoming active and standby OC-12 signals. If the active OC-12 signal
fails, the LNCTL circuit pack broadcasts a switch request to the board controller
on the OC48 TRMTR circuit pack via the BCLAN. In the transmit (toward the
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