Circuit Pack Descriptions
7-76 Issue 8.0 July 2002
OC-48 line) direction only, the OC48 TRMTR circuit pack selects the standby
STS-3/3c signal(s) from the standby OC12 (1.3 STD) circuit pack.
High-Speed Protection. 7If an OC-48 signal fails or is degraded, the LNCTL circuit
pack broadcasts a switch request to the board controllers on the OC12 (1.3 STD)
circuit packs via the BCLAN. In the transmit direction, the OC12 (1.3 STD) circuit
packs perform head-end bridges. In the FT-2000 OC-48 Add/Drop-Rings
Terminal, four STS-3/3c signals (each at 155.52 Mb/s) are provided to the OC48
TRMTR A/D circuit packs for lines 1E and 1W. In the receive direction, the OC12
(1.3 STD) circuit packs perform tail-end switches. In the FT-2000 OC-48
Add/Drop-Rings Terminal, selector circuitry on the OC12 (1.3 STD) circuit packs
accept the STS-3/3c signals from the OC48 RCVR A/D circuit pack opposite of
the configured direction.
Dual Ring Interworking Protection. 7TheOC12(1.3STD)circuitpackatthe
primary node of a dual ring interworking application monitors the OC-12 signal
coming from the other ring. If an unprotected incoming OC-12 loss-of-signal or
loss-of-frame condition is detected, the OC12 (1.3 STD) circuit pack notifies the
LNCTL circuit pack. The LNCTL circuit pack broadcasts an automatic switch
request to the board controller on the OC48 TRMTR circuit pack via the BCLAN.
In the add (toward to OC-48 line) direction only, the OC48 TRMTR circuit pack
switches to (selects) the standby 155.52 Mb/s signals (STS-3 tributary) from the
secondary node. This completes the circuit from the secondary node to the
termination node in the ring.
Synchronization Reference Protection. 7Synchronization reference switching is
done by selecting the primary or secondary synchronization reference signal from
the TG3 (DS1) circuit packs. The timing interface circuitry of the OC12 (1.3 STD)
circuit pack monitors these synchronization reference signals and can
autonomously select the primary or secondary. The LNCTL circuit pack can inhibit
this autonomous selection and make its own selection.
When the network element is in the through-timed mode, the OC-12 Timing
Direction parameter determines the high-speed line (1W or 1E) from which the
OC-12 derives its timing. The OC-12 Timing Direction parameter is
user-provisionable via the CIT, and its default value is 1W. This parameter may be
needed when the OC-12 is used to distribute timing to far-end equipment. When
the network element is not through-timed, the OC-12 derives its timing from that
element’s system clock.
Fault Detection Circuitry 7
Monitoring and Testing. 7The board controller circuit monitors all the activities on
the circuit pack. The OC12 (1.3 STD) circuit pack has an in-service and
out-of-service built-in test capability. In-service testing is continuous. If an error
occurs, the board controller reports the error to the LNCTL circuit pack using the
board controller local area network (BCLAN). An out-of-service test is performed
whenever the OC12 (1.3 STD) circuit pack is inserted in a slot or when a reset is
performed.
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