Circuit Pack Descriptions
7-58 Issue 8.0 July 2002
Dual Ring Interworking Protection. 7The OC3 (1.3 STD) circuit pack at the primary
node of a dual ring interworking application monitors the OC-3 signal coming from
the other ring. If an unprotected incoming OC-3 loss-of-signal or loss-of-frame
condition is detected, the OC3 (1.3 STD) circuit pack notifies the LNCTL circuit
pack. The LNCTL circuit pack broadcasts an automatic switch request to the
board controller on the OC48 TRMTR circuit pack via the BCLAN. In the add
(toward to OC-48 line) direction only, the OC48 TRMTR circuit pack switches to
(selects) the standby 155.52 Mb/s signal (STS-3 tributary) from the secondary
node. In Release 7 and later releases, the OC48 TRMTR circuit pack may switch
to (select) the standby 51.84 Mb/s signal (STS-1 tributary) from the secondary
node. This completes the circuit from the secondary node to the termination node
in the ring.
Synchronization Reference Protection. 7Synchronization reference switching is
done by selecting the primary or secondary synchronization reference signal from
the TG3 (DS1) circuit packs. The timing interface circuitry of the OC3 (1.3 STD)
circuit pack monitors these synchronization reference signals and can
autonomously select the primary or secondary. The LNCTL circuit pack can inhibit
this autonomous selection and make its own selection.
Fault Detection Circuitry 7
Monitoring and Testing. 7The board controller circuit monitors all the activities on
the circuit pack. The OC3 (1.3 STD) circuit pack has an in-service and
out-of-service built-in test capability. In-service testing is continuous. If an error
occurs, the board controller reports the error to the LNCTL circuit pack using the
board controller local area network (BCLAN). An out-of-service test is performed
whenever the OC3 (1.3 STD) circuit pack is inserted in a slot or when a reset is
performed.
Loopbacks . 7The OC3 (1.3 STD) circuit pack provides OC-3 and STS-3/3c
loopbacks for fault isolation and remote testing. The OC-3 loopback loops the
input from the OC-3 line back to the output of the OC-3 line via a loop connection
in the low speed STS-3 byte processor. This loopback does not loop the OC-3
DCC overhead channel. The STS-3/3c loopback loops the STS-3/3c signal from
the OC-48 line back to the STS-3/3c signal transmitted toward the OC-48 line via
a loop connection in the OC-3 line STS-3 byte processor. The OC-3 and STS-3/3c
loopback paths include the transmit and receive pointer processors.
These loopbacks are implemented in response to craft interface terminal (CIT)
commands (via the SYSCTL and LNCTL circuit packs) and controlled by the
board controller.
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