Circuit Pack Descriptions
7-64 Issue 8.0 July 2002
In the transmit direction (toward the OC-48 line), the IS3 (1.3 STD) circuit pack
accepts one IS-3 (155.52 Mb/s) non-return-to-zero (NRZ) synchronous optical
network (SONET) compatible optical signal. Fiber access to the IS3 (1.3 STD)
circuit pack is via a fixed
ST
â
-type buildout block and a removable
ST
-type,
FC/PC-type, or SC-type lightguide buildout on the circuit pack faceplate (labeled
IN). Lightguide buildouts are chosen based on the attenuation desired, the type of
connector interface, and the type of lightguide jumpers (single-mode or
multimode). All factory-equipped IS3 (1.3 STD) circuit packs come with a
removable
ST
-type 0-dB lightguide buildout. When installing or removing
lightguide buildouts, do not pull the beam (front tab) outward. Pulling the beam
(front tab) outward could result in breaking the beam (front tab).
The optical-to-electrical module receives the IS-3 signal, converts it to an
electrical STS-3/3c signal (155.52 Mb/s), and sends it to a timing recovery circuit.
The timing recovery circuit recovers a 155.52 MHz clock signal from the STS-3/3c
signal and retimes the STS-3/3c signal with the recovered clock signal. The
STS-3/3c and clock signals are then sent to the IS-3 line STS-3 byte processor.
The IS-3 line STS-3 byte processor descrambles and demultiplexes the STS-3/3c
signal into three STS-1 signals (51.84 Mb/s) and outputs the three STS-1 signals
and a common clock signal to the transmit pointer processor.
The transmit pointer processor performs frequency adjustment and pointer
processing on the three received STS-1 signals. This synchronizes the STS-1
signals to the 51.84 MHz system clock. The 51.84 MHz clock signal is obtained by
dividing the 155.52 MHz from the Timing Generator, Stratum 3 - DS1 [TG3 (DS1)]
circuit packs by three. The divide-by-three circuit is part of the low speed STS-3
byte processor. The three STS-1 signals are then sent to the low speed STS-3
byte processor.
The low speed STS-3 byte processor scrambles and multiplexes the three STS-1
signals back to one STS-3/3c signal (155.52 Mb/s). The high speed interface
distributes the STS-3/3c signal to the OC48 TRMTR circuit packs.
Receive Direction . 7In the receive direction (toward the IS-3 line), the high speed
interface accepts the STS-3/3c signal (155.52 Mb/s) from an OC48 RCVR circuit
pack and sends it to a timing recovery circuit. The timing recovery circuit recovers
a 155.52 MHz clock signal from the STS-3/3c signal and retimes the STS-3/3c
signal with the recovered clock signal. The STS-3/3c and clock signals are then
sent to the low speed STS-3 byte processor. The low speed STS-3 byte processor
descrambles and demultiplexes the STS-3/3c signal into three STS-1 signals
(51.84 Mb/s) and outputs the three STS-1 signals and a common clock signal to
the receive pointer processor.
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