Circuit Pack Descriptions
7-120 Issue 8.0 July 2002
Jitter Reduction Circuit. 7The jitter reduction circuit reduces the jitter on the
selected reference input before it enters the digital phase-locked loop circuit.
Digital Phase-Locked Loop Circuit. 7The digital phase-locked loop (DPLL) circuit
consists of a digital counter, a microcontroller, a digital-to-analog converter, and a
51.84 MHz ovenized, voltage-controlled crystal oscillator. The microcontroller and
software determine the loop parameters and loop performance, as well as
reference monitoring and switching functions. The microcontroller periodically
reads phase information contained in the digital counter. This information is used
by the software to determine phase error and control the frequency output of the
oscillator. The phase-locked loop incorporates a microprocessor as the loop filter.
Software in this processor determines the loop bandwidth and performance, as
well as monitoring and switching functions.
Output Driver Circuits. 7The output driver circuits generate and distribute the
following types of timing signals:
■ A 155.52 MHz signal is distributed to the OC48 Transmitter (OC48
TRMTR) and low speed interface circuit packs.
■ A 25.92 MHz cross-coupled reference signal is distributed to the
companion TG3 (DS1) circuit pack.
DS1 Reference Interface Circuit. 7The DS1 reference interface circuit generates
and distributes a 1.544 MHz (DS1) synchronization output signal to the office
BITS clock or other SONET network elements in an office. In the LAA18 TG3
(DS1) circuit pack (Figure 7-35), the DS1 reference interface circuit derives the
DS1 output signal directly from the 25.92 MHz line reference. The DS1 reference
interface circuit of the LAA18 TG3 (DS1) circuit pack also accepts a 51.84 MHz
signal from the digital phase-locked loop circuit to generate DS1 alarm indication
signals (AIS) whenever the line reference is not acceptable.
Protection Circuitry 7
The TG3 (DS1) circuit packs are 1x1 (revertive) protected. When the active TG3
(DS1) circuit pack board controller determines that its clock output is out of
tolerance, it suppresses its timing outputs and signals the LNCTL circuit pack. The
LNCTL circuit pack signals the companion TG3 (DS1) circuit pack of the failed
condition. The suppressed timing outputs cause the transmission circuit packs to
perform a hardware switch to the standby TG3 (DS1) circuit pack.
Timing reference switching is done by selecting the primary or secondary
reference signal (phase locked mode or loop timed mode). In the phase locked
mode, if the primary DS1 reference signal fails, the secondary DS1 reference
signal will be selected. If both DS1 reference signals fail, the TG3 (DS1) circuit
pack holds the on-board oscillator frequency at the last good reference sample
(holdover mode) while the DS1 reference signals are repaired.
In the loop timed mode, if the primary line reference fails, the secondary line
reference is selected. If both line references fail, the TG3 (DS1) circuit pack will
attempt to select the primary DS1 reference (if equipped). If the primary DS1
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