Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 119
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Clocking Architecture
The PHY design requires that a PLL module be used to generate various clocks, and both
global and local clock networks are used to distribute the clock throughout the design. The
PHY also requires one MMCM in the same bank as the PLL. This MMCM compensates for the
insertion delay of the BUFG to the PHY.
The clock generation and distribution circuitry and networks drive blocks within the PHY
that can be divided roughly into four separate, general functions:
• Internal (FPGA) logic
• Write path (output) I/O logic
• Read path (input) and delay I/O logic
• IDELAY reference clock
For DDR3 designs, one MMCM is required for IDELAY reference clock generation. If the
design frequency is > 667 MHz, then IDELAY reference clock is either 300 MHz or 400 MHz
(depending on FPGA speed grade). MIG instantiates one MMCM for 300 MHz and 400 MHz
clock generation.
One MMCM and one PLL are required for the PHY. The PLL is used to generate the clocks for
most of the internal logic, the frequency reference clocks to the phasers, and a
synchronization pulse required for keeping PHY control blocks synchronized in multi-I/O
bank implementations.
For DDR3 SDRAM clock frequencies between 400 MHz and 933 MHz, both the phaser
frequency reference clocks have the same frequency as the memory clock frequency. For
DDR2 or DDR3 SDRAM clock frequencies below 400 MHz, one of the phaser frequency
reference clocks runs at the same frequency as the memory clock and the second frequency
reference clock must be either 2x or 4x the memory clock frequency such that it meets the
range requirement of 400 MHz to 933 MHz. The two phaser frequency reference clocks
must be generated by the same PLL so they are in phase with each other. The block diagram
of the clocking architecture is shown in Figure 1-52. The phase of freq_refclk varies
based on frequency of operation and banks selected for memory interface pins.
• When HP banks are selected for memory interface pins in GUI and the memory
frequencies ≥ 400 MHz, the phase is 337.5°.
• When HP banks are selected for memory interface pins in GUI and the memory
frequencies are between 200–400 MHz (excluding 400 MHz), the phase is 315°.
• For Low Voltage devices when HP banks are selected for memory interface pins in GUI
and the memory frequencies ≥ 400 MHz, the phase is 337.5°.
• For Low Voltage devices when HP banks are selected for memory interface pins in GUI
and the memory frequencies are between 200–400 MHz (excluding 400 MHz), the
phase is 0°.
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English